PM5383-BI PMC-Sierra Inc, PM5383-BI Datasheet
PM5383-BI
Specifications of PM5383-BI
Related parts for PM5383-BI
PM5383-BI Summary of contents
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... Saturn User Network Interface Device Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet PM5383 S/UNI-12xJET For J2/E3/T3 Data Sheet Preliminary Issue No. 2: July 2002 Preliminary 1 ...
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Legal Information Copyright Copyright 2002 PMC-Sierra, Inc. All rights reserved. The information in this document is proprietary and confidential to PMC-Sierra, Inc., and for its customers’ internal use. In any event, no part of this document may be reproduced or ...
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Contacting PMC-Sierra PMC-Sierra 8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: +1 (604) 415-6000 Fax: +1 (604) 415-6200 Document Information: Corporate Information: Technical Support: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Revision History Issue No. Issue Date 1 July 2002 1 October 2001 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Details of Change Updated ...
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Table of Contents Legal Information........................................................................................................................... 2 Copyright................................................................................................................................. 2 Disclaimer ............................................................................................................................... 2 Trademarks ............................................................................................................................. 2 Patents 2 Contacting PMC-Sierra.................................................................................................................. 3 Revision History............................................................................................................................. 4 Table of Contents........................................................................................................................... 5 List of Figures .............................................................................................................................. 11 List of Tables................................................................................................................................ 16 1 Definitions ............................................................................................................................. 19 2 ...
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Description ............................................................................................................................ 44 7.1 Serial Framer/Transmitter Processing ...................................................................... 44 7.2 ATM/Bit-HDLC Processing ........................................................................................ 44 7.3 SONET/SDH Processing .......................................................................................... 45 7.4 System Side Interfaces ............................................................................................. 46 8 Pin Diagram .......................................................................................................................... 47 8.1 Pin Diagram (Bottom View) ....................................................................................... 47 8.2 Pin ...
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SONET/SDH Bit Error Rate Monitor (SBER) .......................................................... 119 10.5 SONET/SDH Alarm Reporting Controller (SARC) .................................................. 119 10.6 Receive Time Slot Interchange (RX STI) ................................................................ 119 10.7 DS3/E3 Desynchronizer (D3E3MD)........................................................................ 120 10.8 DS3/E3 Jitter Attenuator (JAT) ................................................................................ 122 10.9 DS3 ...
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SMDS PLCP Layer Transmitter (SPLT) .................................................................. 160 10.41 Transmit Cell Processor (TXCP) ............................................................................. 161 10.42 Transmit POS Frame Processor (TXFP) ................................................................ 161 10.43 Transmit Bit HDLC Cell Processor (TXFP) ............................................................. 163 10.44 Transmit UTOPIA Level 2 ATM Interface ................................................................ ...
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POS-PHY Level 3 Data Structures.......................................................................... 230 13.21 Resetting the RXFF and TXFF FIFOs..................................................................... 231 13.22 Servicing Interrupts ................................................................................................. 231 13.23 Using the Performance Monitoring Features .......................................................... 232 13.24 Using the Internal FDL Transmitter ......................................................................... 233 13.25 Using the Internal ...
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Transmit Section and Line DCC.............................................................................. 284 14.22 Transmit Path Overhead ......................................................................................... 284 14.23 Receive SONET/SDH Interface .............................................................................. 286 14.24 Transmit SONET/SDH Interface ............................................................................. 287 15 Absolute Maximum Ratings ................................................................................................ 288 16 Normal Operating Conditions.............................................................................................. 289 17 Power Information............................................................................................................... 290 ...
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List of Figures Figure 1 Typical S/UNI-12xJET ATM (UTOPIA Level 2) Application........................................ 36 Figure 2 Typical S/UNI-12xJET ATM (UTOPIA or POS-PHY Level 3) Application............................................................................................................................. 37 Figure 3 Typical S/UNI-12xJET Packet (POS-PHY Level 2) Application.................................. 37 Figure 4 Typical S/UNI-12xJET OC-12 ...
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Figure 31 Byte HDLC CRC Generator .................................................................................... 162 Figure 32 Bit HDLC Frame Format ......................................................................................... 163 Figure 33 Bit HDLC CRC Generator ....................................................................................... 164 Figure 34 Boundary Scan Architecture ................................................................................... 167 Figure 35 TAP Controller Finite State Machine....................................................................... 168 Figure ...
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Figure 66 32-Wide, 109 Byte Packet Data Structure .............................................................. 231 Figure 67 Typical Data Frame................................................................................................. 238 Figure 68 Example Multi-Packet Operational Sequence ........................................................ 238 Figure 69 PRGD Pattern Generator ........................................................................................ 240 Figure 70 STS-12 (STM-4) on RTOH/TTOH........................................................................... 242 Figure 71 ...
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Figure 102 Receive POS Level 3 System Interface Timing .................................................... 277 Figure 103 Incoming Parallel TelecomBus Timing.................................................................. 278 Figure 104 Outgoing Parallel TelecomBus.............................................................................. 279 Figure 105 RTOH output timing .............................................................................................. 280 Figure 106 RTOH and ROHFP output timing.......................................................................... 280 Figure ...
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Figure 138 Transmit Serial Interface Timing ........................................................................... 318 Figure 139 Receive Serial Interface Timing ............................................................................ 319 Figure 140 DS3 Jitter Tolerance ............................................................................................. 321 Figure 141 DS3 Mapping Wander MTIE ................................................................................. 321 Figure 142 DS3 Pointer Wander MTIE (Single Pointer Adjustment) ...
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List of Tables Table 1 Supported Serial Operating Formats ........................................................................... 22 Table 2 PLM-P, UNEQ-P and PDI-P Defects Declaration ...................................................... 117 Table 3 Expected PDI Defect Based on PDI and PDI Range Values..................................... 118 Table 4 J2 Framer Multi-frame Format.................................................................................... ...
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Table 33 Recommended BERM settings for OC-12 and different BER rates, meeting Bellcore and ITU requirements. ............................................................................ 249 Table 34 DS3 Receive Overhead Bits..................................................................................... 256 Table 35 G.751 E3 Receive Overhead Bits ............................................................................ 257 Table 36 G.832 E3 Receive Overhead ...
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Table 68 Transmit Serial Interface (Figure 138) ..................................................................... 318 Table 69 Receive Serial Interface (Figure 139) ...................................................................... 318 Table 70 DS3 Serial Interface Timing Characteristics ............................................................. 320 Table 71 E3 Serial Interface Timing Characteristics ................................................................ 322 Table 72 Transmit Auxiliary ...
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Definitions The following table defines the abbreviations for the S/UNI-12xJET. Term Definition AIS Alarm Indication Signal ASSP Application Specific Standard Product ATM Asynchronous Transfer Mode BER Bit Error Rate BIP Byte Interleaved Parity CBI Common Bus Interface CMOS Complementary ...
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Term Definition J2-TRAN J2 Transmitter JAT Digital Jitter Attenuator JTAG Joint Test Action Group LAIS Line AIS also referred to as AIS-L LAN Local Area Network LCD Loss of Cell Delineation LCD Loss of Cell Delineation LCV Line Code Violation ...
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Term Definition RXCP Receive ATM Cell Processor RXFP Receive Packet over SONET Frame Processor SARC SONET/SDH Alarm Reporting Controller SBER SONET/SDH Bit Error Monitoring SD Signal Degrade (alarm) SDH Synchronous Digital Hierarchy SF Signal Fail SMDS Switched Multi-Megabit Data Service ...
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Features 2.1 General · Single chip 12-channel ATM User Network Interface operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s conforming to AF-PHY-0054.000, AF-PHY-0034.000 , and AF- PHY-0029.000. Each line can be individually configured for the desired rate and ...
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Single chip ATM and packet process capable of processing rates up to STS-12c/STM-4-4c payloads. · Implements the ATM Forum User Network Interface Specification AF-UNI-0010.02 and the ATM physical layer for Broadband ISDN according to ITU-T Recommendation I.432 series on ...
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System Side Interface · Provides a UTOPIA Level 2 compatible 16-bit wide System Interface (clocked MHz) with parity support for ATM applications. · Provides a POS-PHY Level 2™ 16-bit System Interface (clocked MHz) ...
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Provides ATM framing using cell delineation. ATM cell delineation may optionally be disabled to allow passing of all cell bytes regardless of cell delineation status. · Extracts ATM cells from the arbitrary STS-1/STM-0/STS-3c/STM-1/STS-12c/STM-4-4c SONET/SDH payloads using ATM cell delineation. ...
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Serial Transmitter · Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm insertion, and diagnostic features. In addition, far end alarm channel codes may be inserted, and an integral HDLC transmitter is provided to insert the ...
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The Transmit Byte HDLC Processor · Supports any packet based link layer protocol using byte synchronous HDLC framing like PPP, HDLC and Frame Relay. · Insert frames into arbitrary STS-1/STM-0/STS-3c/STM-1/STS-12c/STM-4-4c SONET/SDH payloads. · Performs self-synchronous POS data scrambling using ...
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Absorbs pointer movements and DS3 / E3 payload bit stuffs in an elastic store, and controls outgoing clock phase using the smooth clock generator circuit with selectable lock and fast lock modes of operation. · Detects elastic store FIFO ...
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Extracts and serializes on dedicated pins the data communication channels (D1-D3 or D4- D12) and inserts the corresponding signals into the transmit stream. · Extracts and filters the automatic protection switch (APS) channel (K1, K2) bytes into internal registers. ...
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Counts received path remote error indications (REI) for performance monitoring purposes. Optionally inserts the path REI count into the path status byte (G1) based on bit or block BIP-8 errors detected in the receive path. · Provides automatic transmit ...
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Applications · ATM or SMDS Switches, Multiplexers, and Routers · SONET/SDH Mux E3/DS3 Tributary Interfaces · PDH Mux J2/E3/DS3 Line Interfaces · DS3/E3/J2 Digital Cross Connect Interfaces · DS3/E3/J2 PPP Internet Access Interfaces · DS3/E3/J2 Frame Relay Interfaces · ...
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References 1. ATM Forum, af-uni-0010.02, ATM User-Network Interface Specification, V3.1 September 1994. 2. ATM Forum, af-phy-0029.000, 6,312 Kbps UNI Specification, Version 1.0, June 1995. 3. ATM Forum, af-phy-0034.000, E3 Public UNI, August 1995. 4. ATM Forum, af-phy-0039.000, UTOPIA Level ...
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Bell Communications Research, TA-TSY-000772 - Generic System Requirements in Support of Switched Multi-Megabit Data Service, Issue 3, October 1989 and Supplement 1, December 1990. 20. Bell Communications Research, TR-TSV-000773 - Local Access System Generic Requirements, Objectives, and Interface in ...
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ITU-T Recommendation G.707 - Network Node Interface For The Synchronous Digital Hierarchy, October 2000. 35. ITU-T Recommendation G.751, GENERAL ASPECTS OF DIGITAL TRANSMISSION SYSTEMS -TERMINAL EQUIPMENTS; Digital multiplex equipments operating at the third order bit rate of 34 368 ...
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ITU-T Recommendation I.432.3, ISDN user-network interfaces – Layer 1 Recommendations; B-ISDN B-ISDN user-network interface – Physical layer specification: 1544 kbit/s and 2048 kbit/s operation, February 1999. 48. ITU-T Recommendation I.432.4, ISDN user-network interfaces – Layer 1 Recommendations; B-ISDN B-ISDN ...
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Application Examples The S/UNI® 12xJET device provides a complete physical layer solution for the aggregation, transport and termination channels of DS3/E3 and J2 protocols. The S/UNI 12xJET provides substantial functional flexibility due to its broad ...
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Figure 2 Typical S/UNI-12xJET ATM (UTOPIA or POS-PHY Level 3) Application Serial I/O DS3/ LIU # 1 E3/J2 Serial I/O DS3/ LIU # 12 E3/J2 The S/UNI-12xJET can be configured as packet and/or ATM physical layer device. On the line ...
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The S/UNI-12xJET can be configured as DS3 and/or E3 transport device, for SONET/SDH applications. On the line side, it connects to an external SERDES with clock synthesis and clock recovery using the duplex 8-bit 77.76MHz interface. On the system side, ...
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Figure 7 Typical S/UNI-12xJET 48xDS3/E3 Aggregation Metro Core MSPP Application TM TSE PM5372-BI CA615781A M0011 PHILIPINES The S/UNI-12xJET can be used to fully or partially terminate SONET/SDH applications requiring ATM, POS, DS3 or E3. As shown in Figure 4, the ...
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Figure 9 Typical S/UNI-12xJET Sub-rate Processing Application O/E OC-12 Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Sub-Rate Processor FPGA SERDES Interface SERDES Sub-Rate ...
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Block Diagram Figure 10 S/UNI-12xJET Block Diagram OHCLK OHCH[3:0] TOHVAL TOHFA TOHINS TOH TPHVAL TPHFA TPHINS TPH ROHVAL ROHFA ROH RPHVAL RPHFA RPH FRAC[1:0] RSCLK/EFBWCLK[11:0] RDATO/EFBWDAT[11:0] RFPO/RMFPO/EFBWEN[11:0] ROVRHD/EFBWDREQ[11:0] FRMSTAT[11:0] TICLK/IFBWCLK[11:0] TDATI/IFBWDAT[11:0] TIOHM/TFPI/TMFPI/IFBWEN[11:0] TFPO/TMFPO[11:0] RNEG/RLCV/ROHM/IFBWEN[11:0] RPOS/RDATI/IFBWDAT[11:0] RCLK/IFBWCLK[11:0] TNEG/TOHM/EFBWEN[11:0] TPOS/TDATO/EFBWDAT[11:0] TCLK/EFBWCLK[11:0] ...
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Figure 11 S/UNI-12xJET Diagnostic Loopbacks OHCLK OHCH[3:0] TOHVAL TOHFA TOHINS TOH TPHVAL TPHFA TPHINS TPH ROHVAL ROHFA ROH RPHVAL RPHFA RPH FRAC[1:0] RSCLK/EFBWCLK[11:0] RDATO/EFBWDAT[11:0] RFPO/RMFPO/EFBWEN[11:0] ROVRHD/EFBWDREQ[11:0] FRMSTAT[11:0] TICLK/IFBWCLK[11:0] TDATI/IFBWDAT[11:0] TIOHM/TFPI/TMFPI/IFBWEN[11:0] TFPO/TMFPO[11:0] RNEG/RLCV/ROHM/IFBWEN[11:0] RPOS/RDATI/IFBWDAT[11:0] RCLK/IFBWCLK[11:0] TNEG/TOHM/EFBWEN[11:0] TPOS/TDATO/EFBWDAT[11:0] TCLK/EFBWCLK[11:0] DS3_REFCLK E3_REFCLK REF8KI ...
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Figure 12 S/UNI-12xJET Line Loopbacks OHCLK OHCH[3:0] TOHVAL TOHFA TOHINS TOH TPHVAL TPHFA TPHINS TPH ROHVAL ROHFA ROH RPHVAL RPHFA RPH FRAC[1:0] RSCLK/EFBWCLK[11:0] RDATO/EFBWDAT[11:0] RFPO/RMFPO/EFBWEN[11:0] ROVRHD/EFBWDREQ[11:0] FRMSTAT[11:0] TICLK/IFBWCLK[11:0] TDATI/IFBWDAT[11:0] TIOHM/TFPI/TMFPI/IFBWEN[11:0] TFPO/TMFPO[11:0] RNEG/RLCV/ROHM/IFBWEN[11:0] RPOS/RDATI/IFBWDAT[11:0] RCLK/IFBWCLK[11:0] TNEG/TOHM/EFBWEN[11:0] TPOS/TDATO/EFBWDAT[11:0] TCLK/EFBWCLK[11:0] DS3_REFCLK E3_REFCLK REF8KI ...
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... Description 7.1 Serial Framer/Transmitter Processing The PM5383 S/UNI-12xJET is a 12-channel ATM and packet physical layer processor with integrated DS3, E3, and J2 framers. HDLC sub-layer DS1, DS3, E1, and E3 processing is supported. Both ATM cell delineation and bit-synchronous HDLC for packet delineation are supported. Mixtures of DS3 and E3 modes are allowed, as well as mixtures of ATM/PLCP, HDLC, and bit-synchronous HDLC packet delineation ...
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In the PLCP receive direction, framing, path overhead extraction and cell extraction are provided. BIP-8 error events, frame octet error events and far end block error events are accumulated. In the PLCP transmit direction, the S/UNI-12xJET provides overhead insertion using ...
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System Side Interfaces The S/UNI-12xJET supports UTOPIA Level 2, UTOPIA Level 3, POS-PHY Level 2 and POS- PHY Level 3 system interfaces for ATM and HDLC packet data. ATM cells are buffered in 4- cell per-channel FIFOs in Level ...
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Pin Diagram The S/UNI-12xJET is packaged in a 580-pin TSBGA package having a body size of 35mm by 35mm and a pin pitch of 1mm. 8.1 Pin Diagram (Bottom View VSS ...
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Pin Diagram Top Right (Bottom View VSS TOH TPHINS B NC VSS TOHINS C FRAC[1] FRAC[0] VSS D REF8KO VDD REF8KI E SMODE[0] VDD VDD F TDAT[29] TDAT[31] SMODE[2] G TDAT[25] TDAT[26] TDAT[27] H TDAT[21] ...
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Pin Diagram Bottom Right (Bottom View) V TADR[4] TFCLK RDAT[31] W RDAT[30] RDAT[29] RDAT[28] Y RDAT[25] RDAT[24] RDAT[23] AA RDAT[21] RDAT[20] RDAT[19] AB RDAT[16] RDAT[15] VDD AC RDAT[14] RDAT[13] VSS AD RDAT[12] RDAT[11] RDAT[10] AE RDAT[8] RDAT[7] RDAT[6] AF ...
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Pin Diagram Bottom Left (Bottom View) RNEG_RLCV TCLK_EFBW VSS VDDI _ROHM_IFB CLK[9] WEN[10] TPOS_TDAT RNEG_RLCV RPOS_RDATI VSS O_EFBWDAT _ROHM_IFB _IFBWDAT[10 [9] WEN[9] ] RDATO_EFB TNEG_TOHM TICLK_IFBW RCLK_IFBW WDAT[9] _EFBWEN[9] CLK[9] CLK[10] RFPO_RMFP TFPO_TMFP TDATI_IFBW RCLK_IFBW TDATI_IFBW O_EFBWEN[ O[9] DAT[9] ...
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Pin Diagram Top Left (Bottom View TIOHM_TFPI_ RFPO_RMFP TPOS_TDAT TNEG_TOHM ROVRHD_EF TMFPI_IFBW O_EFBWEN[ O_EFBWDAT _EFBWEN[2] BWDREQ[2] EN[2] 3] TCLK_EFBW TFPO_TMFP RDATO_EFB TCLK_EFBW FRMSTAT[2] CLK[2] O[2] WDAT[3] TPOS_TDAT RSCLK_EFB RSCLK_EFB O_EFBWDAT FRMSTAT[3] WCLK[2] WCLK[3] [2] RDATO_EFB ...
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Pin Description 9.1 Modes, Clocking and Frame Pulses Pin Name Type SMODE[0] Input SMODE[1] SMODE[2] SPMACHB Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product ...
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Pin Name Type FRAC[0] Input FRAC[1] OHCLK Input OHCH[0] Output OHCH[1] OHCH[2] OHCH[3] DS3_ REFCLK Input E3_REFCLK Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product ...
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Pin Name Type REF8KI Input REF8KO Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. D32 Reference 8 kHz Input (REF8KI). ...
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Transmit Serial Line Side Interface Pin Name Type TCLK[0] I/O TCLK[1] TCLK[2] TCLK[3] TCLK[4] TCLK[5] TCLK[6] TCLK[7] TCLK[8] TCLK[9] TCLK[10] TCLK[11] TPOS[0] Output TPOS[1] TPOS[2] TPOS[3] TPOS[4] TPOS[5] TPOS[6] TPOS[7] TPOS[8] TPOS[9] TPOS[10] TPOS[11] TDATO[0] Output TDATO[1] TDATO[2] TDATO[3] ...
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Pin Name Type TNEG[0] Output TNEG[1] TNEG[2] TNEG[3] TNEG[4] TNEG[5] TNEG[6] TNEG[7] TNEG[8] TNEG[9] TNEG[10] TNEG[11] TOHM[0] Output TOHM[1] TOHM[2] TOHM[3] TOHM[4] TOHM[5] TOHM[6] TOHM[7] TOHM[8] TOHM[9] TOHM[10] TOHM[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Receive Serial Line Side Interface Pin Name Type RCLK[0] Input RCLK[1] RCLK[2] RCLK[3] RCLK[4] RCLK[5] RCLK[6] RCLK[7] RCLK[8] RCLK[9] RCLK[10] RCLK[11] RPOS[0] Input RPOS[1] RPOS[2] RPOS[3] RPOS[4] RPOS[5] RPOS[6] RPOS[7] RPOS[8] RPOS[9] RPOS[10] RPOS[11] RDATI[0] Input RDATI[1] RDATI[2] RDATI[3] ...
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Pin Name Type RNEG[0] Input RNEG[1] RNEG[2] RNEG[3] RNEG[4] RNEG[5] RNEG[6] RNEG[7] RNEG[8] RNEG[9] RNEG[10] RNEG[11] RLCV[0] Input RLCV[1] RLCV[2] RLCV[3] RLCV[4] RLCV[5] RLCV[6] RLCV[7] RLCV[8] RLCV[9] RLCV[10] RLCV[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Pin Name Type ROHM[0] Input ROHM[1] ROHM[2] ROHM[3] ROHM[4] ROHM[5] ROHM[6] ROHM[7] ROHM[8] ROHM[9] ROHM[10] ROHM[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet ...
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Transmit Serial Overhead Insertion Pin Name Type TOHVAL Output TOHFA Output TOHINS Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function ...
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Pin Name Type TOH Input TPHVAL Output TPHFA Output TPHINS Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. A33 Transmit ...
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Pin Name Type TPH Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. C31 Transmit PLCP Overhead Data (TPH). TPH contains ...
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Receive Serial Overhead Extraction Pin Name Type ROHVAL Output ROHFA Output ROH Output RPHVAL Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet ...
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Pin Name Type RPHFA Output RPH Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. A30 Receive PLCP Overhead Frame Alignment ...
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Transmit TelecomBus Interface Pin Name Type OCLK Input OD[0] Tristate Output OD[1] OD[2] OD[3] OD[4] OD[5] OD[6] OD[7] ODP Tristate Output OPL Tristate Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, ...
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Pin Name Type OJ0J1 Output OALARM Output OJ0REF Input OSTSEN Output OCLK_REF Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. ...
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Receive TelecomBus Interface Pin Name Type ICLK Input ID[0] Input ID[1] ID[2] ID[3] ID[4] ID[5] ID[6] ID[7] IDP Input IPL Input IJ0J1 Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue ...
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Pin Name Type IALARM Input ICLK_REF Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AC2 Incoming Alarm Status (IALARM). IALARM ...
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Transmit SONET/SDH Interface Pin Name Type PTCLK Input POUT[0] Output POUT[1] POUT[2] POUT[3] POUT[4] POUT[5] POUT[6] POUT[7] TSFPI Input TSFPO Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ...
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Receive SONET/SDH Interface Pin Name Type PICLK Input PIN[0] Input PIN[1] PIN[2] PIN[3] PIN[4] PIN[5] PIN[6] PIN[7] FPIN Input RSFPO Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ...
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Pin Name Type OOF Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AJ1 Out of Frame Indication (OOF). The active ...
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Transmit SONET/SDH Overhead Insertion Pin Name Type TOHCLK Output TOHFP Output TTOH Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function ...
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Pin Name Type TTOHEN Input TPOH Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AN6 Transmit Transport Overhead Insert Enable ...
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Pin Name Type TPOHEN Input TPOHRDY Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AL6 Transmit Path Overhead Insert Enable ...
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Pin Name Type TSLDCLK Output TSLD Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AM4 Transmit section or Line Data ...
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Receive SONET/SDH Overhead Extraction Pin Name Type ROHCLK Output ROHFP Output RTOH Output RPOH Output RPOHEN Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product ...
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Pin Name Type SALM Output RALM Output B3E Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AK1 Section Alarm Indication ...
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Pin Name Type RSLDCLK Tristate Output RSLD Tristate Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AJ2 Receive section or ...
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Transmit Serial Auxiliary Interface Pin Name Type TICLK[0] Input TICLK[1] TICLK[2] TICLK[3] TICLK[4] TICLK[5] TICLK[6] TICLK[7] TICLK[8] TICLK[9] TICLK[10] TICLK[11] TDATI[0] Input TDATI[1] TDATI[2] TDATI[3] TDATI[4] TDATI[5] TDATI[6] TDATI[7] TDATI[8] TDATI[9] TDATI[10] TDATI[11] Proprietary and Confidential to PMC-Sierra, Inc., ...
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Pin Name Type TIOHM[0] Input TIOHM[1] TIOHM[2] TIOHM[3] TIOHM[4] TIOHM[5] TIOHM[6] TIOHM[7] TIOHM[8] TIOHM[9] TIOHM[10] TIOHM[11] TFPI[0] Input TFPI[1] TFPI[2] TFPI[3] TFPI[4] TFPI[5] TFPI[6] TFPI[7] TFPI[8] TFPI[9] TFPI[10] TFPI[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Pin Name Type TMFPI[0] Input TMFPI[1] TMFPI[2] TMFPI[3] TMFPI[4] TMFPI[5] TMFPI[6] TMFPI[7] TMFPI[8] TMFPI[9] TMFPI[10] TMFPI[11] TFPO[0] Output TFPO[1] TFPO[2] TFPO[3] TFPO[4] TFPO[5] TFPO[6] TFPO[7] TFPO[8] TFPO[9] TFPO[10] TFPO[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal ...
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Pin Name Type TMFPO[0] Output TMFPO[1] TMFPO[2] TMFPO[3] TMFPO[4] TMFPO[5] TMFPO[6] TMFPO[7] TMFPO[8] TMFPO[9] TMFPO[10] TMFPO[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet ...
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Receive Serial Auxiliary Interface Pin Name Type RSCLK[0] I/O RSCLK[1] RSCLK[2] RSCLK[3] RSCLK[4] RSCLK[5] RSCLK[6] RSCLK[7] RSCLK[8] RSCLK[9] RSCLK[10] RSCLK[11] RDATO[0] Output RDATO[1] RDATO[2] RDATO[3] RDATO[4] RDATO[5] RDATO[6] RDATO[7] RDATO[8] RDATO[9] RDATO[10] RDATO[11] Proprietary and Confidential to PMC-Sierra, Inc., ...
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Pin Name Type RFPO[0] Output RFPO[1] RFPO[2] RFPO[3] RFPO[4] RFPO[5] RFPO[6] RFPO[7] RFPO[8] RFPO[9] RFPO[10] RFPO[11] RMFPO[0] Output RMFPO[1] RMFPO[2] RMFPO[3] RMFPO[4] RMFPO[5] RMFPO[6] RMFPO[7] RMFPO[8] RMFPO[9] RMFPO[10] RMFPO[11] ROVRHD[0] I/O ROVRHD[1] ROVRHD[2] ROVRHD[3] ROVRHD[4] ROVRHD[5] ROVRHD[6] ROVRHD[7] ROVRHD[8] ROVRHD[9] ...
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Pin Name Type FRMSTAT[0] Output FRMSTAT[1] FRMSTAT[2] FRMSTAT[3] FRMSTAT[4] FRMSTAT[5] FRMSTAT[6] FRMSTAT[7] FRMSTAT[8] FRMSTAT[9] FRMSTAT[10] FRMSTAT[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet ...
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Ingress Flexible Bandwidth Interface Pin Name Type IFBWCLK[0] Input IFBWCLK[1] IFBWCLK[2] IFBWCLK[3] IFBWCLK[4] IFBWCLK[5] IFBWCLK[6] IFBWCLK[7] IFBWCLK[8] IFBWCLK[9] IFBWCLK[10] IFBWCLK[11] IFBWDAT[0] Input IFBWDAT[1] IFBWDAT[2] IFBWDAT[3] IFBWDAT[4] IFBWDAT[5] IFBWDAT[6] IFBWDAT[7] IFBWDAT[8] IFBWDAT[9] IFBWDAT[10] IFBWDAT[11] Proprietary and Confidential to PMC-Sierra, Inc., ...
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Pin Name Type IFBWEN[0] Input IFBWEN[1] IFBWEN[2] IFBWEN[3] IFBWEN[4] IFBWEN[5] IFBWEN[6] IFBWEN[7] IFBWEN[8] IFBWEN[9] IFBWEN[10] IFBWEN[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet ...
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Egress Flexible Bandwidth Interface Pin Name Type EFBWCLK[0] Input EFBWCLK[1] EFBWCLK[2] EFBWCLK[3] EFBWCLK[4] EFBWCLK[5] EFBWCLK[6] EFBWCLK[7] EFBWCLK[8] EFBWCLK[9] EFBWCLK[10] EFBWCLK[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP ...
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Pin Name Type EFBWDREQ[0] Input EFBWDREQ[1] EFBWDREQ[2] EFBWDREQ[3] EFBWDREQ[4] EFBWDREQ[5] EFBWDREQ[6] EFBWDREQ[7] EFBWDREQ[8] EFBWDREQ[9] EFBWDREQ[10] EFBWDREQ[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet ...
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Pin Name Type EFBWDAT[0] Output EFBWDAT[1] EFBWDAT[2] EFBWDAT[3] EFBWDAT[4] EFBWDAT[5] EFBWDAT[6] EFBWDAT[7] EFBWDAT[8] EFBWDAT[9] EFBWDAT [10] EFBWDAT [11] EFBWEN[0] Output EFBWEN[1] EFBWEN[2] EFBWEN[3] EFBWEN[4] EFBWEN[5] EFBWEN[6] EFBWEN[7] EFBWEN[8] EFBWEN[9] EFBWEN[10] EFBWEN[11] Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Transmit System Side Interface Pin Name Type TFCLK Input TDAT[0] Input TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15] TDAT[16] TDAT[17] TDAT[18] TDAT[19] TDAT[20] TDAT[21] TDAT[22] TDAT[23] TDAT[24] TDAT[25] TDAT[26] TDAT[27] TDAT[28] ...
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Pin Name Type TPRTY Input TENB Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. P33 The UTOPIA transmit bus parity ...
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Pin Name Type TSOC Input TSOP TEOP Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. The POS-PHY transmit write enable ...
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Pin Name Type TERR Input TMOD[0] Input TMOD[1] TSX Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. R33 The POS-PHY ...
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Pin Name Type STPA Output TADR[0] Input TADR[1] TADR[2] TADR[3] TADR[4] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. T32 The ...
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Pin Name Type TCA Output PTPA Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. T33 The UTOPIA transmit cell available (TCA) ...
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Receive System Side Interface Pin Name Type RFCLK Input RDAT[0] Output RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RDAT[16] RDAT[17] RDAT[18] RDAT[19] RDAT[20] RDAT[21] RDAT[22] RDAT[23] RDAT[24] RDAT[25] RDAT[26] RDAT[27] RDAT[28] ...
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Pin Name Type RPRTY Output RENB Input Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AF30 The UTOPIA receive parity (RPRTY) ...
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Pin Name Type RSOC Output RSOP REOP Output RERR Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AG34 The UTOPIA ...
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Pin Name Type RMOD[0] Output RMOD[1] RSX Output RADR[0] Input RADR[1] RADR[2] RADR[3] RADR[4] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function ...
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Pin Name Type RCA Output RVAL RCA Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. AH31 The UTOPIA Level 3 ...
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Pin Name Type RPA Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, Issue 2 SUNI-12xJET ASSP Telecom Standard Product Data Sheet Pin Function No. The POS-PHY receive packet available (RPA) provides a direct ...
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Microprocessor Interface Signals Pin Name Type CSB Input WRB Input RDB Input D[0] I/O D[1] D[2] D[3] D[4] D[5] D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ ...
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Pin Name Type A[0] Input A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] Input RSTB Input ALE Input INTB Output Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: ...
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JTAG Interface Signals Pin Name Type TCK Input TMS Input TDI Input TDO Output TRSTB Input 9.20 Power and Ground Pin Name Type ATB[1] Analog ATB[2] AVD1 Analog AVD2 Power Proprietary and Confidential to PMC-Sierra, Inc., and for its ...
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Pin Name Type AVS1 Analog AVS2 Power VDDI Digital Power VDD Digital Power VSS Digital Power NC No Connect Notes on Pin Description: 1. All digital inputs and bi-directional signals present minimum capacitive loading and operate at TTL logic levels ...
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Due to ESD protection structures in the pads it is necessary to exercise caution when powering a device up or down. ESD protection devices behave as diodes between power supply pins and from I/O pins to power supply pins. ...
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Functional Description 10.1 Receive Regenerator and Multiplexer Processor (RRMP) The Receive Regenerator and Multiplexer Processor (RRMP) block extracts and processes the transport overhead of the received data stream. The RRMP frames to the data stream by operating with an ...
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The RRMP calculates the line BIP-8 error detection codes on the de-scrambled line overhead and synchronous payload envelope bytes of the constituent STS-1 (STM-0). The line BIP-8 code is based on a bit interleaved parity calculation using even parity. The ...
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Figure 13 STS-12 (STM-4) on RTOH First order of transmission D10 Unused bytes National bytes The RRMP optionally serially outputs ...
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The second algorithm is ITU compliant. The algorithm detects trace identifier unstable (TIU) defect and trace identifier mismatch (TIM) defect byte trail trace message. The current trail trace message is stored in the captured page ...
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The transition between states will be consecutive events (indications), e.g., three consecutive AIS indications to go from the NORM_state to the AIS_state. The kind and number of consecutive indications activating a transition is chosen such that the behavior is stable ...
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DEC_IND: INV_POINT: not any of the above (i.e.: not NORM_POINT, not NDF_ENABLE, not AIS_IND, not INC_IND and not DEC_IND). NEW_POINT: disabled NDF + ss + offset value in range 782 but not Notes on event (indication) definitions: ...
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NDF_ENABLE AIS_IND INV_POINT NDF_ENABLE Notes on transitions indicated in state diagram: 1. The transitions from NORM_state to NORM_state do not represent state changes but imply offset changes EQ_NEW_POINT takes precedence over ...
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The transitions between the states will be consecutive events (indications), e.g. three consecutive AIS indications to go from the CONC_state to the AISC_state. The kind and number of consecutive indications activating a transition is chosen such that the behavior is ...
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Notes on transitions indicated in state diagram: 1. “Consecutive event counters are reset to zero on a change of state. LOPC is declared on entry to the LOPC_state after eight consecutive pointers with values other than concatenation indications. Path AIS ...
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The RHPP also monitors the path signal label byte (C2) to detect path payload label mismatch (PLM-P) defect. PLM-P is declared when the accepted PSL does not match the expected PSL according to Table 2. PLM-P is removed when the ...
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Table 3 Expected PDI Defect Based on PDI and PDI Range Values PDI DPI range register value register value 00000 Disable Enable 00001 Disable Enable 00010 Disable Enable 00011 Disable Enable 00100 Disable Enable 00101 Disable Enable 00110 Disable Enable ...
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RDI-P is declared when bit 5 of the G1 byte is set high for five or ten consecutive frames (selectable by the PRDI10 bit in the configuration register). RDI-P is removed when bit 5 of the G1 byte is set ...
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The RX_STI is not a complete Time Slot Interchange in that it does not re-order timeslots; however, the RX_STI does allow any channel to receive data on any of the timeslots in chronological order starting from the master timeslot. ...
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When SONET defects is detected or the AISGEN normal mode register bit is set high, the extracted DS3 / E3 payload is overwritten by an Alarm Indication Signal (AIS) and the outgoing clock is held constant at 44.736 MHz in ...
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The D3E3MD may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the D3E3MD. Access to these registers is ...
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The SHIFT option can be enabled to force the PLL to auto-center the FIFO fill level. The FIFO peak fill and empty levels are measured periodically and the PLL is pushed in the direction such that the FIFO average fill ...
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The JAT may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the JAT. Access to these registers is ...
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Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the T3-FRMR. The maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of ...
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The T3-FRMR extracts the entire DS3 overhead (56 bits per M-frame) using the ROH output, along with the OHCLK, and ROHFA outputs. The T3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts ...
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The General Purpose Communication Channel byte and presents it to the RDLC when the RNETOP bit in the S/UNI-12xJET Data Link and FERF Control register is logic 0 The byte is also brought out on the ROH output with ...
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J2 Framer The J2-FRMR integrates circuitry to decode a unipolar or B8ZS encoded signal and frame to the resulting 6312 Kbps J2 bit stream. Having found frame, the J2-FRMR extracts a variety of overhead and data-link information from the ...
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Table 4 J2 Framer Multi-frame Format Bit # 1-8 ... Frm. 1 TS1[1:8] ... Frm. 2 TS1[1:8] ... Frm. 3 TS1[1:8] ... Frm. 4 TS1[1:8] ... TS1 .. TS96 : TS97, TS98: Frame Alignment Signal x1, x2, x3: ...
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J2 LOF is declared when 7 or more consecutive multi-frames with erred framing patterns are received. The J2 LOF is cleared when 3 or more consecutive multi-frames with correct framing patterns are received. A framing algorithm that takes into account ...
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Figure 19 Framing Algorithm (CRC_REFR = 0) Reset or Out of Frame Using this algorithm, the J2-FRMR will, on average, find frame in 5.07ms when starting the search in the worst possible position, given a 10 When the CRC_REFR bit ...
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Figure 20 Framing Algorithm (CRC_REFR = 1) Reset or Out of Fram e Using this algorithm, the J2-FRMR will find frame in 10.22ms, on average when starting the search in the worst possible position, given a 10 algorithm will reject ...
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J2 extended Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of ...
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Bit-oriented codes (BOCs) are received on the FEAC channel as 16-bit sequences each consisting of 8 ones, a zero, 6 code bits, and a trailing zero ("111111110xxxxxx0"). BOCs are validated when repeated at least 10 times. The RBOC can be ...
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The SPLR frames to DS1, DS3, E1, and G.751 E3 based PLCP frames with maximum average reframe times of 635 µs, 22 µs, 483 µs, and 32 µs respectively. Framing is declared (out of frame is removed) upon finding 2 ...
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When a correct HCS is found, the ATMF locks on the particular cell boundary and assumes the PRESYNC state. This state verifies that the previously detected HCS pattern was not a false indication. If the HCS pattern was a false ...
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Receive Cell Processor (RXCP) The Receive Cell Processor (RXCP) Block integrates circuitry to support scrambled or unscrambled cell payloads, scrambled or unscrambled cell headers, header check sequence (HCS) verification, idle cell filtering, and performance monitoring. When interacting with the ...
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The Performance Monitor consists of 8-bit saturating HCS error event counter and a 24-bit saturating receive cell counter. The error counter accumulates HCS errors. The 24-bit receive cell counter counts all cells written into the receive FIFO. Filtered cells are ...
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In the event of a FIFO overflow caused by the FIFO being full while a packet is being received, the packet is marked with an error so it can be discarded by the system. Subsequent bytes associated with this now ...
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Performance Monitor The Performance Monitor consists of four 16-bit saturating error event counters and one 24-bit saturating received good packet counter. One of the error event counters accumulates FCS errors. The second error event counter accumulates minimum length violation ...
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The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-16.ISO-3309 or CRC-32 function. Figure 25shows a CRC encoder block diagram using the generating polynomial g( size and has a generating g(X) ...
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Receive UTOPIA Level 2 ATM Interface The UTOPIA Level 2 compatible interface accepts a read clock (RFCLK) and read enable signal (RENB). The interface indicates the start of a cell (RSOC) and the receive cell available status (RCA) when ...
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The UTOPIA Level 3 compatible interface accepts a read clock (RFCLK) and read enable signal (RENB). The RADR[3:0] bus with RCA is used to poll the channel FIFOs for fill status. As well, channels are selected using the RADR[3:0] and ...
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Pseudo-Random Sequence Generator/Detector (PRGD) The Pseudo-Random Sequence Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver and analyzer. Two types of test patterns, pseudo-random and repetitive, conform to ITU-T O.151. The PRGD can be programmed to generate ...
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Table 6 Maximum Line REI Errors per Transmit Frame SONET/SDH STS-3/STM-1 STS-12/STM-4 The TRMP serially inputs all the transport overhead (TOH) bytes from the TTOH port. The TOH bytes must be input in the same order that they are transmitted ...
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Table 7 TOH Insertion Priority BYTE HIGHEST priority STS-1/STM-0 # (J0Z0INCEN=1) Z0 STS-1/STM-0 # (J0Z0INCEN= D1- D4- D12 S1 Z1 Proprietary and Confidential to PMC-Sierra, Inc., and for ...
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BYTE HIGHEST priority Nation al Unuse d PLD The Z0DEF register bit defines the Z0/NATIONAL growth bytes for row #1. When Z0DEF is set to logic one, the Z0/NATIONAL bytes are defined according to ITU. When Z0DEF ...
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The TRMP calculates the line BIP-8 error detection codes on the transmit data stream. One line BIP-8 error detection code is calculated for each of the constituent STS-1 (STM-0). The line BIP-8 byte is calculated on the unscrambled bytes of ...
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The THPP serially inputs all the path overhead (POH) bytes from the TPOH port. The POH bytes must be input in the same order that they are transmitted (J1, B3, C2, G1, F2, H4, F3, K3 and N1). TOHCLK is ...
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The FIFO read and write addresses are monitored. Pointer justification requests will be made to the Pointer Generator based on the proximity of the addresses relative to FIFO thresholds. The Pointer Generator schedules a pointer increment event if the FIFO ...
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Figure 27 Pointer Generation State Diagram INC inc_ind PI_AIS AIS AIS_ind The following events, indicated in the state diagram, are defined ES_lowerT: ES filling is below the lower threshold + previous inc_ind, dec_ind or NDF_enable more than three frames ago. ...
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PI_LOP LOP state PI_NORM NORM state Note 1 A frame offset discontinuity occurs if an incoming NDF enabled is received overflow/underflow occurred. The autonomous transitions indicated in the state diagram are defined ...
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A maskable interrupt is activated to indicate any change in the synchronization status. 10.32 Transmit STS-1 Time Slot Interchange (TX_STI) The TX_STI determines which STS-1 Timeslots are to be provisioned for a particular channel. An incoming ADD bus is provided ...
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The D3E3MA supports a variety of mapping structures (AU3 or TUG3) and perform either DS3 or E3 mapping. These mapping modes can be set via the normal mode register bits DS3E3B and AU3TUG3B. Regardless of the incoming data source (AIS ...
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Typical D3E3MA jitter transfer characteristics are show in the Figure 29. Figure 29 Typical D3E3MA Jitter Transfer -10 -20 -30 -40 -50 -60 -70 The system (including the D3E3MA) intrinsic jitter, pointer jitter, jitter tolerance, mapping wander, ...
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A valid pair of P-bits is automatically calculated and inserted by the T3-TRAN. When C-bit parity mode is selected, the path parity bits and far end block error (FEBE) indications are automatically inserted. When enabled for C-bit parity operation, the ...
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Inserts the Timing Marker bit via a register bit. 8. Inserts the Network Operator (NR) byte from the TDPR block when the TNETOP bit in the Channel Data Link and FERF/RAI Control register is logic 1; otherwise, the NR ...
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Inserts payload AIS or physical layer AIS through microprocessor programmable register bits. 6. Inserts RAI over the m-bits, overwriting HDLC frames, by using the XBOC block or through automatic activation upon detection of certain remote alarm conditions. The J2-TRAN ...
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Facility Data Link Transmitter (TDPR) The Facility Data Link Transmitter (TDPR) provides a serial data link for the C-bit parity path maintenance data link in DS3, the serial Network Operator byte or the General Purpose data link in G.832 ...
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SMDS PLCP Layer Transmitter (SPLT) The SMDS PLCP Layer Transmitter (SPLT ) Block integrates circuitry to support DS1, DS3, E1, and G.751 E3 based PLCP frame insertion. The SPLT automatically inserts the framing (A1, A2) and path overhead identification ...
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Transmit Cell Processor (TXCP) The Transmit Cell Processor (TXCP) Block integrates circuitry to support ATM cell payload scrambling, header check sequence (HCS) generation, and idle/unassigned cell generation. The TXCP scrambles the cell payload field using the self synchronizing scrambler ...
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In the event of a FIFO underflow caused by the FIFO being empty while a packet is being transmitted, the packet is aborted by transmitting the Abort Sequence. The Abort Sequence consists of an Escape Control character (0x7D) followed by ...
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Byte Stuffing The POS Frame generator provides transparency by performing byte stuffing. This operation is done after the FCS calculation. Two characters are being escaped, the Flag Sequence (0x7E) and the Escape Character itself (0x7D). When a character is ...
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The CRC algorithm for the frame checking sequence (FCS) field is either a CRC-16.ISO-3309 or CRC-32 function. Figure 33 shows a CRC encoder block diagram using the generating polynomial g( size and has a generating ...
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The TSOP signal is used to identify the start of a packet; the TPA signal notifies the system side that the transmit FIFO is not full (the POS processor will not start transmitting a packet until a programmable number of ...
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The POS-PHY Level 3 compatible interface accepts a write clock (TFCLK), a write enable signal (TENB), the start of packet (TSOP) indication, the end of packet (TEOP) indication, erred packet (TERR) indication and the parity bit (TPRTY) when data is ...
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Figure 34 Boundary Scan Architecture TDI TMS TRSTB TCK The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets ...
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Figure 35 TAP Controller Finite State Machine TRSTB=0 Test-Logic-Reset 1 0 Run-Test-Idle 0 Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by ...
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Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, ...
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EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by ...
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Normal Mode Register Description Please refer to Document PMC-2012190 “Saturn User Network Interface (12xJET) Device for J2/E3/T3 Data Sheet Register Description” for register description. Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, ...
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Test Features Description Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode ...
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Parameter Version Number Part Number Manufacturer’s Identification Code Device Identification Table 12 Boundary Scan Register Pin/Enable FRAC[0] FRAC[1] REF8KI OEB_REF8KO REF8KO SMODE[0] SMODE[1] SMODE[2] TDAT[31] TDAT[30] TDAT[29] TDAT[28] TDAT[27] TDAT[26] TDAT[25] TDAT[24] TDAT[23] TDAT[22] TDAT[21] TDAT[20] TDAT[19] TDAT[18] TDAT[17] TDAT[16] ...
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Pin/Enable TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TPRTY TENB TSOC_TSOP TEOP TERR TMOD[0] TMOD[1] TSX OEB_STPA STPA OEB_TCA_PTPA TCA_PTPA TADR[0] TADR[1] TADR[2] TADR[3] TADR[4] TFCLK OEB_RDAT[31] RDAT[31] OEB_RDAT[30] RDAT[30] OEB_RDAT[29] RDAT[29] OEB_RDAT[28] RDAT[28] OEB_RDAT[27] RDAT[27] OEB_RDAT[26] RDAT[26] OEB_RDAT[25] ...
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Pin/Enable RDAT[25] OEB_RDAT[24] RDAT[24] OEB_RDAT[23] RDAT[23] OEB_RDAT[22] RDAT[22] OEB_RDAT[21] RDAT[21] OEB_RDAT[20] RDAT[20] OEB_RDAT[19] RDAT[19] OEB_RDAT[18] RDAT[18] OEB_RDAT[17] RDAT[17] OEB_RDAT[16] RDAT[16] OEB_RDAT[15] RDAT[15] OEB_RDAT[14] RDAT[14] OEB_RDAT[13] RDAT[13] OEB_RDAT[12] RDAT[12] OEB_RDAT[11] RDAT[11] OEB_RDAT[10] RDAT[10] OEB_RDAT[9] RDAT[9] OEB_RDAT[8] RDAT[8] OEB_RDAT[7] RDAT[7] OEB_RDAT[6] RDAT[6] ...
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Pin/Enable OEB_RDAT[5] RDAT[5] OEB_RDAT[4] RDAT[4] OEB_RDAT[3] RDAT[3] OEB_RDAT[2] RDAT[2] OEB_RDAT[1] RDAT[1] OEB_RDAT[0] RDAT[0] OEB_RPRTY RPRTY OEB_RSOC_RSOP RSOC_RSOP OEB_REOP REOP OEB_RERR RERR OEB_RMOD[0] RMOD[0] OEB_RMOD[1] RMOD[1] OEB_RSX RSX OEB_RCA_RPA RCA_RPA OEB_RCA_RVAL RCA_RVAL RADR[0] RADR[1] RADR[2] RADR[3] RADR[4] RENB RFCLK Proprietary and ...
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Pin/Enable DS3_REFCLK E3_REFCLK RCLK_IFBWCLK[6] RPOS_RDATI_IFBWDAT[ 6] RNEG_RLCV_ROHM_IFB WEN[6] TICLK_IFBWCLK[6] TDATI_IFBWDAT[6] TIOHM_TFPI_TMFPI_IFB WEN[6] OEB_TCLK_EFBWCLK[6] TCLK_EFBWCLK[6] OEB_TPOS_TDATO_EFB WDAT[6] TPOS_TDATO_EFBWDAT [6] OEB_TNEG_TOHM_EFB WEN[6] TNEG_TOHM_EFBWEN[6 ] OEB_TFPO_TMFPO[6] TFPO_TMFPO[6] OEB_RSCLK_EFBWCLK[ 6] RSCLK_EFBWCLK[6] OEB_RDATO_EFBWDAT[ 6] RDATO_EFBWDAT[6] OEB_RFPO_RMFPO_EFB WEN[6] RFPO_RMFPO_EFBWEN[ 6] OEB_ROVRHD_EFBWDR EQ[6] ROVRHD_EFBWDREQ[6] OEB_FRMSTAT[6] FRMSTAT[6] Proprietary ...
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Pin/Enable OEB_FRMSTAT[7] FRMSTAT[7] OEB_ROVRHD_EFBWDR EQ[7] ROVRHD_EFBWDREQ[7] OEB_RFPO_RMFPO_EFB WEN[7] RFPO_RMFPO_EFBWEN[ 7] OEB_RDATO_EFBWDAT[ 7] RDATO_EFBWDAT[7] OEB_RSCLK_EFBWCLK[ 7] RSCLK_EFBWCLK[7] OEB_TFPO_TMFPO[7] TFPO_TMFPO[7] OEB_TNEG_TOHM_EFB WEN[7] TNEG_TOHM_EFBWEN[7 ] OEB_TPOS_TDATO_EFB WDAT[7] TPOS_TDATO_EFBWDAT [7] OEB_TCLK_EFBWCLK[7] TCLK_EFBWCLK[7] TIOHM_TFPI_TMFPI_IFB WEN[7] TDATI_IFBWDAT[7] TICLK_IFBWCLK[7] RNEG_RLCV_ROHM_IFB WEN[7] RPOS_RDATI_IFBWDAT[ 7] RCLK_IFBWCLK[7] RCLK_IFBWCLK[8] RPOS_RDATI_IFBWDAT[ 8] ...
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Pin/Enable RNEG_RLCV_ROHM_IFB WEN[8] TICLK_IFBWCLK[8] TDATI_IFBWDAT[8] TIOHM_TFPI_TMFPI_IFB WEN[8] OEB_TCLK_EFBWCLK[8] TCLK_EFBWCLK[8] OEB_TPOS_TDATO_EFB WDAT[8] TPOS_TDATO_EFBWDAT [8] OEB_TNEG_TOHM_EFB WEN[8] TNEG_TOHM_EFBWEN[8 ] OEB_TFPO_TMFPO[8] TFPO_TMFPO[8] OEB_RSCLK_EFBWCLK[ 8] RSCLK_EFBWCLK[8] OEB_RDATO_EFBWDAT[ 8] RDATO_EFBWDAT[8] OEB_RFPO_RMFPO_EFB WEN[8] RFPO_RMFPO_EFBWEN[ 8] OEB_ROVRHD_EFBWDR EQ[8] ROVRHD_EFBWDREQ[8] OEB_FRMSTAT[8] FRMSTAT[8] OEB_FRMSTAT[9] FRMSTAT[9] OEB_ROVRHD_EFBWDR EQ[9] ROVRHD_EFBWDREQ[9] Proprietary ...
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Pin/Enable OEB_RFPO_RMFPO_EFB WEN[9] RFPO_RMFPO_EFBWEN[ 9] OEB_RDATO_EFBWDAT[ 9] RDATO_EFBWDAT[9] OEB_RSCLK_EFBWCLK[ 9] RSCLK_EFBWCLK[9] OEB_TFPO_TMFPO[9] TFPO_TMFPO[9] OEB_TNEG_TOHM_EFB WEN[9] TNEG_TOHM_EFBWEN[9 ] OEB_TPOS_TDATO_EFB WDAT[9] TPOS_TDATO_EFBWDAT [9] OEB_TCLK_EFBWCLK[9] TCLK_EFBWCLK[9] TIOHM_TFPI_TMFPI_IFB WEN[9] TDATI_IFBWDAT[9] TICLK_IFBWCLK[9] RNEG_RLCV_ROHM_IFB WEN[9] RPOS_RDATI_IFBWDAT[ 9] RCLK_IFBWCLK[9] RCLK_IFBWCLK[10] RPOS_RDATI_IFBWDAT[ 10] RNEG_RLCV_ROHM_IFB WEN[10] TICLK_IFBWCLK[10] TDATI_IFBWDAT[10] TIOHM_TFPI_TMFPI_IFB ...
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Pin/Enable OEB_TCLK_EFBWCLK[10 ] TCLK_EFBWCLK[10] OEB_TPOS_TDATO_EFB WDAT[10] TPOS_TDATO_EFBWDAT [10] OEB_TNEG_TOHM_EFB WEN[10] TNEG_TOHM_EFBWEN[1 0] OEB_TFPO_TMFPO[10] TFPO_TMFPO[10] OEB_RSCLK_EFBWCLK[ 10] RSCLK_EFBWCLK[10] OEB_RDATO_EFBWDAT[ 10] RDATO_EFBWDAT[10] OEB_RFPO_RMFPO_EFB WEN[10] RFPO_RMFPO_EFBWEN[ 10] OEB_ROVRHD_EFBWDR EQ[10] ROVRHD_EFBWDREQ[10 ] OEB_FRMSTAT[10] FRMSTAT[10] OEB_FRMSTAT[11] FRMSTAT[11] OEB_ROVRHD_EFBWDR EQ[11] ROVRHD_EFBWDREQ[11 ] OEB_RFPO_RMFPO_EFB WEN[11] RFPO_RMFPO_EFBWEN[ 11] ...
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Pin/Enable OEB_RSCLK_EFBWCLK[ 11] RSCLK_EFBWCLK[11] OEB_TFPO_TMFPO[11] TFPO_TMFPO[11] OEB_TNEG_TOHM_EFB WEN[11] TNEG_TOHM_EFBWEN[1 1] OEB_TPOS_TDATO_EFB WDAT[11] TPOS_TDATO_EFBWDAT [11] OEB_TCLK_EFBWCLK[11 ] TCLK_EFBWCLK[11] TIOHM_TFPI_TMFPI_IFB WEN[11] TDATI_IFBWDAT[11] TICLK_IFBWCLK[11] RNEG_RLCV_ROHM_IFB WEN[11] RPOS_RDATI_IFBWDAT[ 11] RCLK_IFBWCLK[11] TTOH TTOHEN TPOH TPOHEN OEB_TOHCLK TOHCLK OEB_TOHFP TOHFP OEB_TPOHRDY TPOHRDY OEB_TSLDCLK TSLDCLK TSLD OEB_ROHCLK ...
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Pin/Enable ROHFP OEB_RTOH RTOH OEB_RPOH RPOH OEB_RPOHEN RPOHEN OEB_SALM SALM Notes 1. Each output has its own output enable (OEB*) 2. When set high, INTB will be set to high impedance 3. FRAC[0] is the first bit in the boundary ...
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Figure 37 Output Cell (OUT_CELL) EXTEST Output or Enable from system logic IDOODE SHIFT-DR I.D. code bit CLOCK-DR UPDATE-DR Scan Chain In Figure 38 Bi-directional Cell (IO_CELL) EXTEST OUTPUT from internal logic IDCODE SHIFT-DR INPUT from pin I.D. code bit ...
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Figure 39 Layout of Output Enable and Bi-directional Cells OUTPUT ENABLE from internal logic (0 = drive) INPUT to internal logic OUTPUT from internal logic Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use. Document No.: PMC-2010376, ...
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Operation 13.1 System Interface Configurations The System Interface can be configured UTOPIA Level 2, POS-PHY Level 2, UTOPIA Level 3, or POS-PHY Level 3 interface. Table 13 System Interface Configurations Mode UTOPIA Level 2 POS-PHY Level ...
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Table 14 System Interface Basic Configurations Operating S/UNI-12xJET Channel Register Values (Values in Hexadecimal) Mode Receive Address(es) ATM (UL3 – 0x1810* Utopia Level 3) 0x1818, 0x1819, (POS3 – POS- 0x181A, 0x181B* PHY Level 3) ATM Slice (For 0x0107** slice N, ...
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Operating S/UNI-12xJET Channel Register Values (Values in Hexadecimal) Mode Framer/ TX (For slice N, Address add N*0x200) 0x0004 0x0008 0x0030 0x0061 T3 M23 ADM 0x0003 0x0004 0x0008 0x0030 0x0061 T3 C-bit PLCP 0x0003 0x0004 0x0008 0x0030 0x0061 T3 M23 PLCP ...
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Operating S/UNI-12xJET Channel Register Values (Values in Hexadecimal) Mode Framer/ TX (For slice N, Address add N*0x200) E3 G.751 ADM 0x0003 0x0004 0x0008 0x0038 0x0039 0x0061 E3 G.751 PLCP 0x0003 0x0004 0x0008 0x0038 0x0039 0x0061 E3 G.751 framer 0x0003 only* ...
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Operating S/UNI-12xJET Channel Register Values (Values in Hexadecimal) Mode Framer/ TX (For slice N, Address add N*0x200) External Framer 0x0003 ADM* 0x0008 0x0061 * In Framer Only Modes, 0x009B needs to be set to 0x0001, in all other modes 0x009B ...
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Figure 40 Clear Channel PDH Over SONET/SDH Data Path Serial Interface TJAT Jitter Attenuator TX STI STS-1 Timeslot Interchange RX STI STS-1 Timeslot Interchange 13.3.2 PDH Framer Only PDH Framer Only mode uses the serial and auxiliary serial interfaces. The ...
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Figure 41 PDH Framer Only Data Path Serial Interface TJAT RJAT Jitter Jitter Attenuator Attenuator 13.3.3 Cell/Packet over PDH Cell/Packet over PDH uses the serial interfaces and the system interfaces (Utopia Level2/3, and POS-PHY Level 2/3). The transmit path starts ...
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The receive path starts at the receive serial interface, through the RJAT, through the FRMR, through the ATM & PLCP Framer and RXCP or only through the RXFP to the receive system interface. The RJAT may be bypassed via register ...
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Transmit path is from the transmit auxiliary serial interface, through the AUX FRMR and/or the TRAN, through the DS3E3 Mapper to SONET/SDH. The Auxiliary FRMR may be used for monitoring purposes while the data path passes through the TRANS. Receive ...
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The transmit path starts at the transmit system interface, through the TXCP or TXFP based on ATM or Packet/HDLC mode, through the ATM & PLCP transmitter, the egress flexible bandwidth interface. The SPLT ATM and PLCP transmitter are used to ...
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Figure 44 Cell/Packet Delineation Only Data Path Serial Interface 13.3.6 Cell/Packet over SONET/SDH Cell/Packet over SONET/SDH mode uses the SONET/SDH interfaces and the system interfaces (Utopia Level2/3, and POS-PHY Level 2/3). Note that only ATM and Packet modes are available ...
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The receive path starts at the SONET/SDH interface, progresses through the RXCP or the RXFP to the receive system interface. Each slice may be configured to process an STS-1/STM- STS-3c/STM STS- 12c/STM-4-4c payload using the TX ...
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The transmit path starts at the transmit system interface, through the TXCP or TXFP based on ATM or Packet/HDLC mode, through the ATM & PLCP transmitter, through the TRAN, through the DS3E3 Mapper to SONET/SDH. The receive path starts from ...
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The transmit path starts at the transmit system interface, through the TXCP or TXFP based on ATM or Packet/HDLC mode, through the ATM & PLCP transmitter, the egress flexible bandwidth interface. The SPLT ATM and PLCP transmitter are used to ...
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Figure 47 Cell/Packet Over PDH Over SONET/SDH With External Processing Data Path Serial Interface TX STI STS-1 Timeslot Interchange RX STI STS-1 Timeslot Interchange Table 16 Slice Operation Basic Configurations Operating Mode (For slice N add N*0x200 to Address) Clear ...