LH28F400BVN-BL85 Sharp, LH28F400BVN-BL85 Datasheet
LH28F400BVN-BL85
Related parts for LH28F400BVN-BL85
LH28F400BVN-BL85 Summary of contents
Page 1
... Flash Memory LH28F400BVN-BL85 Date Jul. 21. 1998 ...
Page 2
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
Page 3
INTRODUCTION.............................................................. 3 1.1 Features ........................................................................ 3 1.2 Product Overview......................................................... 3 2 PRINCIPLES OF OPERATION........................................ 6 2.1 Data Protection............................................................. 6 3 BUS OPERATION ............................................................ 7 3.1 Read.............................................................................. 7 3.2 Output Disable.............................................................. 7 3.3 Standby......................................................................... 7 3.4 Deep Power-Down ....................................................... 7 ...
Page 4
... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F400BVN-BL85 offers two levels of protection: absolute protection with V at GND, selective hardware boot block locking ...
Page 5
... V connection to 2.7V, 3. 1.2 Product Overview The LH28F400BVN-BL85 is a high-performance 4M-bit SmartVoltage Flash memory organized as 512K-byte of 8 bits or 256K-word of 16 bits. The 512K-byte/256K-word of data is arranged in two 8K-byte/4K-word boot blocks, six 8K-byte/4K-word parameter blocks and seven 64K- byte/32K-word main blocks which are individually erasable in-system ...
Page 6
DQ Output Buffer Comparator Y Input Decoder Buffer X Address Latch Decoder Address Counter Figure 1. Block Diagram ...
Page 7
Symbol Type ADDRESS INPUTS: Addresses are internally latched during a write cycle Byte Select Address. Not used in ×16 mode INPUT Row Address. Selects 1 of 2048 word lines ...
Page 8
... PRINCIPLES OF OPERATION The LH28F400BVN-BL85 SmartVoltage Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power- down mode (see Bus Operations), the device defaults to read array mode ...
Page 9
... SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU ...
Page 10
Read Identifier Codes Operation The read identifier codes operation manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms ...
Page 11
Mode Notes Read 7 Output Disable Standby Deep Power-Down 3 Read Identifier Codes 7 Write 5,6,7 Mode Notes Read 7 Output Disable Standby Deep Power-Down 3 Read Identifier Codes 7,8 Write 5,6,7 NOTES: 1. Refer to DC Characteristics. When V ...
Page 12
... RP Either 40H or 10H are recognized by the WSM as the word/byte write setup. 7. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. Table 4. Command Definitions ...
Page 13
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
Page 14
Word/Byte Write Command Word/byte write is executed by a two-cycle command sequence. Word/byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of ...
Page 15
Word/Byte Write Suspend Command The Word/Byte Write Suspend word/byte write interruption to read data in other flash memory locations. Once the word/byte write process starts, writing the Word/Byte Write Suspend command requests that the WSM suspend the word/byte write ...
Page 16
WSMS ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS ...
Page 17
Start Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 ...
Page 18
Start Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No 0 Suspend SR.7= Word/Byte Write Yes 1 Full Status Check if Desired Word/Byte Write Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See ...
Page 19
Start Write B0H Read Status Register 0 SR. SR.6= Block Erase Completed 1 Read or Read Word/Byte Write Word/Byte Write? Read Array Data Word/Byte Write Loop No Done? Yes Write D0H Write FFH Read Array Data Block Erase ...
Page 20
Start Write B0H Read Status Register 0 SR. Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH Word/Byte Write Read Array Data Resumed Figure 8. Word/Byte Write Suspend/Resume Flowchart ...
Page 21
... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
Page 22
RP# Transitions CC PP Block erase and word/byte write are not guaranteed if V falls outside of a valid V range, V PPH1/2 valid V range, or RP# V CC1/2/3/4 error is detected, ...
Page 23
ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase and Word/Byte Write.................................0°C to +70°C Temperature under Bias ...................... -10°C to +80°C Storage Temperature ................................ -65°C to +125°C Voltage On Any Pin (except ...
Page 24
AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
Page 25
DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Word/Byte Write CCW CC ...
Page 26
Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during PPLK PP Normal Operations V V ...
Page 27
AC CHARACTERISTICS - READ-ONLY OPERATIONS Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# ...
Page 28
Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t CE# to Output in Low Z ELQX ...
Page 29
Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/Q) (DQ - PHQV V ...
Page 30
Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) ...
Page 31
AC CHARACTERISTICS - WRITE OPERATIONS Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP#V Setup to WE# ...
Page 32
Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t RP# V Setup to WE# Going High PHHWH HH t ...
Page 33
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( RP#( ...
Page 34
ALTERNATIVE CE#-CONTROLLED WRITES Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP#V Setup to CE# Going High ...
Page 35
Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t RP# V Setup to CE# Going High PHHEH HH t ...
Page 36
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( RP#( ...
Page 37
RESET OPERATIONS Device Device State Busy V IH RP#( 2.7V/3.3V/ RP#( Sym. Parameter RP# Pulse Low Time t (If RP# is tied this PLPH CC specification ...
Page 38
BLOCK ERASE AND WORD/BYTE WRITE PERFORMANCE Sym. Parameter t Word/Byte 32K word WHQV1 t Write Time Block EHQV1 4K word Block Block Write 32K word Time Block 4K word Block t Block Erase 32K word WHQV2 t Time Block ...
Page 39
Sym. Parameter t Word/Byte Write Time 32K word Block WHQV1 t 4K word Block EHQV1 Block Write Time 32K word Block 4K word Block t Block Erase Time 32K word Block WHQV2 t 4K word Block EHQV2 Word/Byte Write Suspend ...
Page 40
Flash memory LHFXXVXX family Data Protection Noises having a level exceeding the limit specified in this document may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply, may be interpreted ...
Page 41
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 42
A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
Page 43
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
Page 44
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...