MT48LC1M16A1TG-10S Micron Semiconductor Products, MT48LC1M16A1TG-10S Datasheet

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MT48LC1M16A1TG-10S

Manufacturer Part Number
MT48LC1M16A1TG-10S
Description
16 MEG: x16 SDRAM
Manufacturer
Micron Semiconductor Products
Datasheet

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Part Number:
MT48LC1M16A1TG-10SD
Manufacturer:
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Quantity:
144
FEATURES
• PC100-compliant functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can be
• Internal banks for hiding row access/precharge:
• Programmable burst lengths: 1, 2, 4, 8 or full page
• Auto Precharge Mode
• Self Refresh and Adaptable Auto Refresh Modes
• LVTTL-compatible inputs and outputs
• Single +3.3V 0.3V power supply
OPTIONS
• Architecture
• Plastic Package - OCPL
• Timing
• Refresh
• Part Number Example: MT48LC1M16A1TG-8A S
KEY TIMING PARAMETERS
*CL = CAS (READ) Latency
16 Meg: x16 SDRAM
Z06.pm6 – Rev. 10/97
16Mb (x16) SDRAM PART NUMBER
SYNCHRONOUS
DRAM
GRADE
SPEED
PART NUMBER
MT48LC1M16A1TG S
edge of system clock
changed every clock cycle
1 Meg x 16 - 512K x 16 x 2 banks architecture with
- 32ms, 2,048-cycle refresh (15.6 s/row), or
- 64ms, 2,048-cycle refresh (31.2 s/row), or
- 64ms, 4,096-cycle refresh (15.6 s/row)
1 Meg x 16 (512K x 16 x 2 banks)
50-pin TSOP (400 mil)
8ns cycle time ( 125 MHz clock rate)
10ns cycle time ( 100 MHz clock rate)
12ns cycle time ( 83 MHz clock rate)
2K or 4K with
-8A
-10
-12
FREQUENCY
125 MHz
100 MHz
83 MHz
CLOCK
11 row, 8 column addresses per bank
Self Refresh Mode at 64ms
*CL = 2
9ns
9ns
9ns
ACCESS TIME
ARCHITECTURE
1 Meg x 16 (512K x 16 x 2 banks)
*CL = 3
7.5ns
6ns
9ns
MARKING
SETUP
TIME
2ns
3ns
3ns
1M16
-8A
-10
-12
TG
S
HOLD
TIME
1ns
1ns
1ns
1
MT48LC1M16A1 S - 512K x 16 x 2 banks
GENERAL DESCRIPTION
dom access memory containing 16,777,216 bits. It is inter-
nally configured as a dual 512K x 16 DRAM with a synchro-
nous interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the 512K x 16 bit banks is
organized as 2,048 rows by 256 columns by 16 bits. Read and
write accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a programmed
Note: The # symbol indicates signal is active LOW.
The 16Mb SDRAM is a high-speed CMOS dynamic ran-
DQML
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
CAS#
RAS#
VssQ
VccQ
VssQ
VccQ
WE#
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
A10
Vcc
Vcc
BA
A0
A1
A2
A3
PIN ASSIGNMENT (Top View)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50-Pin TSOP
512K x 16 x 2 banks
2K (A0-A10)
256 (A0-A7)
16 MEG: x16
PRELIMINARY
2K or 4K
1 (BA)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
1997, Micron Technology, Inc.
SDRAM
Vss
DQ15
DQ14
VssQ
DQ13
DQ12
VccQ
DQ11
DQ10
VssQ
DQ9
DQ8
VccQ
NC
DQMH
CLK
CKE
NC
A9
A8
A7
A6
A5
A4
Vss

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MT48LC1M16A1TG-10S Summary of contents

Page 1

... MHz clock rate) 10ns cycle time ( 100 MHz clock rate) 12ns cycle time ( 83 MHz clock rate) • Refresh with Self Refresh Mode at 64ms • Part Number Example: MT48LC1M16A1TG-8A S KEY TIMING PARAMETERS SPEED CLOCK ACCESS TIME GRADE ...

Page 2

GENERAL DESCRIPTION (continued) number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE com- mand are ...

Page 3

CKE CLK CONTROL CS# LOGIC WE# CAS# RAS# MODE REGISTER 12 REFRESH ADDRESS CONTROLLER A0-A10 REGISTER REFRESH 11 COUNTER 11 16 Meg: x16 SDRAM Z06.pm6 – Rev. 10/97 FUNCTIONAL BLOCK DIAGRAM 1 Meg x 16 SDRAM BANK 0 ...

Page 4

PIN DESCRIPTIONS TSOP PIN NUMBERS SYMBOL 35 CLK 34 CKE 18 CS# 17, 15, RAS#, WE# Input 16 CAS# 14, 36 DQML, DQMH 19 BA 21-24, 27-32, 20 A0-A10 DQ0- 11, 12, 39, 40, ...

Page 5

FUNCTIONAL DESCRIPTION In general, the SDRAM is a dual 512K x 16 DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x ...

Page 6

A10 Reserved Mode CAS Latency BT *Should program M11, M10 = ensure compatibility with future devices ...

Page 7

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge The DQs will start driving as a result of the clock edge one ...

Page 8

COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables appear following TRUTH TABLE 1 – Commands and DQM Operation (Notes: 1) NAME (FUNCTION) COMMAND ...

Page 9

COMMAND INHIBIT The COMMAND INHIBIT function prevents new com- mands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effec- tively deselected. Operations already in progress are not affected. NO OPERATION (NOP) ...

Page 10

AUTO REFRESH AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is non- persistent must be issued each time a refresh is required. The addressing ...

Page 11

OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the ...

Page 12

READs READ bursts are initiated with a READ command, as shown in Figure 5. The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO ...

Page 13

The 1 Meg x 16 SDRAM uses a pipelined architecture and therefore ...

Page 14

CLK COMMAND ADDRESS DQ CAS Latency = 1 CLK COMMAND ADDRESS DQ CLK COMMAND ADDRESS DQ NOTE: Each READ command may be to either bank. DQM is LOW. RANDOM READ ACCESSES WITHIN A PAGE 16 Meg: x16 SDRAM Z06.pm6 – ...

Page 15

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE burst may ...

Page 16

A fixed-length READ burst may be followed by, or trun- cated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated) and a full-page burst may be truncated with a PRECHARGE command to the same ...

Page 17

AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command, but the advantage of the PRECHARGE command is that it ...

Page 18

WRITEs WRITE bursts are initiated with a WRITE command, as shown in Figure 13. The starting column and bank addresses are provided with the WRITE command and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE ...

Page 19

Figure 16. Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixed-length WRITE burst may be immediately followed by a ...

Page 20

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW ...

Page 21

CLOCK SUSPEND The clock suspend mode occurs when a column access/ burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on ...

Page 22

TRUTH TABLE 2 – CKE (Notes: 1-4) CKE CKE CURRENT STATE n Power-Down Self Refresh Clock Suspend L H Power-Down Self Refresh Clock Suspend H L All Banks Idle All Banks Idle Reading or Writing H H ...

Page 23

TRUTH TABLE 3 – Current State Bank n - Command to Bank n (Notes: 1-6; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle L ...

Page 24

NOTES (continued): 5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an AUTO REFRESH command and ...

Page 25

TRUTH TABLE 4 – Current State Bank n - Command to Bank m (Notes: 1-6, 8; notes appear below and on next page) CURRENT STATE CS# RAS# CAS# WE# Any Idle ...

Page 26

NOTES (continued): 3. Current state definitions: Idle: The bank has been precharged and Row Active: A row in the bank has been activated and accesses and no register accesses are in progress. Read: A READ burst has been initiated, with ...

Page 27

ABSOLUTE MAXIMUM RATINGS* Voltage Supply CC CC Relative to V .................................................... -1V to +4.6V SS Voltage on Inputs I/O Pins Relative to V .................................................... -1V to +4.6V SS Operating Temperature, T (ambient) .......... 0 ...

Page 28

CAPACITANCE PARAMETER Input Capacitance: CLK Input Capacitance: All other input-only pins Input/Output Capacitance: DQs ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Notes 11 + CHARACTERISTICS PARAMETER Access time from CLK ...

Page 29

AC FUNCTIONAL CHARACTERISTICS (Notes 11 PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input ...

Page 30

NOTES 1. All voltages referenced This parameter is sampled MHz dependent on output loading and cycle rates. CC Specified values are obtained ...

Page 31

INITIALIZE AND LOAD MODE REGISTER ( ( ) ) CLK ( ( CKH t CKS ( ( ( ( ) ) ) ) CKE ( ( ( ( ) ) ) ...

Page 32

CK CLK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP 2 DQM ADDRESS BANK(S) High-Z DQ Two clock cycles Precharge all All banks idle, enter active banks. power-down mode. TIMING PARAMETERS ...

Page 33

CLK t CKS t CKH CKE t CKS t CKH t CMS t CMH COMMAND READ NOP t CMS t CMH 3 DQM COLUMN m A0-A9 2 ( ...

Page 34

CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP 1 DQM ADDRESS BANK(S) High Precharge all active banks. TIMING PARAMETERS -8A -10 SYMBOL* MIN MAX MIN MAX ...

Page 35

CLK t CK CKE t CKS t CKH t CMS t CMH COMMAND PRECHARGE NOP 1 DQM ADDRESS BANK(S) High Precharge all active banks. TIMING PARAMETERS -8A -10 SYMBOL* MIN MAX MIN MAX ...

Page 36

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ROW A10 DISABLE AUTO PRECHARGE ...

Page 37

CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 ...

Page 38

ALTERNATING BANK READ ACCESSES CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 ...

Page 39

CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP READ t CMS 3 DQM COLUMN m A0-A9 ROW ( ROW ...

Page 40

CK CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 DISABLE AUTO PRECHARGE ...

Page 41

WRITE – WITHOUT AUTO PRECHARGE t CK CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ROW A10 DISABLE AUTO PRECHARGE t ...

Page 42

CK CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 BANK ...

Page 43

ALTERNATING BANK WRITE ACCESSES t CK CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP t CMS 3 DQM A0-A9 ROW ENABLE AUTO PRECHARGE ROW A10 t AS ...

Page 44

CL CLK CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP 2 DQM A0-A9 ROW ROW A10 BANK DQ t RCD ...

Page 45

CK CLK t CKS t CKH CKE t CMS t CMH COMMAND ACTIVE NOP 3 DQM A0-A9 ROW ROW A10 BANK DQ t RCD TIMING PARAMETERS ...

Page 46

TYP PIN # .039 (1.00) (2X) 1. All dimensions in inches (millimeters) MAX or typical where noted. NOTE: 2. Package width and length do not ...

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