LRS1393A Sharp, LRS1393A Datasheet
LRS1393A
Related parts for LRS1393A
LRS1393A Summary of contents
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... P P RELIMINARY RODUCT LRS1393A 64M (x16) Boot Block Flash and 8M (x16) SRAM S PECIFICATIONS ® Stacked Chip (Model No.: LRS1393A) Spec No.: MFM2-J14509A Issue Date: July 22, 2002 Integrated Circuits Group ...
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... Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs ...
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... Description Pin Configuration Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.1 Bus Operation 3.2 Simultaneous Operation Modes Allowed with Four Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. Block Diagram Command Definitions for Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.1 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Identifier Codes and OTP Address for Read Operation 5.3 OTP Block Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.4 Functions of Block Lock and Block Lock-Down ...
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... Description The LRS1393A is a combination memory organized as 4,194,304 x16 bit flash memory and 524,288 x16 bit static RAM in one package. Features - Power supply - Operating temperature - Not designed or rated as radiation hardened - 72pin CSP (LCSP072-P-0811) plastic package - Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon ...
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... Pin Configuration INDEX (TOP View) 3 ...
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... Pin Address Inputs (Common F Address Inputs (Flash) F S-A Address Input (SRAM) 17 F-CE Chip Enable Input (Flash) S-CE , S-CE Chip Enable Inputs (SRAM F-WE Write Enable Input (Flash) S-WE Write Enable Input (SRAM) F-OE Output Enable Input (Flash) S-OE Output Enable Input (SRAM) ...
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... Truth Table (1) 3.1 Bus Operation Flash SRAM Notes F-CE Read 3,5 Output 5 Standby L Disable Write 2,3,4,5 Read 5 Output Standby 5 H Disable Write 5 Read 5,6 Reset Power Output 5,6 X Down Disable Write 5,6 Standby 5 H Standby Reset Power 5,6 X Down Notes High-Z = High impedance. Refer to the DC Characteristics. ...
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... Simultaneous Operation Modes Allowed with Four Planes IF ONE Read Read PARTITION IS: Array ID/OTP Read Array X X Read ID/OTP X X Read Status X X Read Query X X Word Program X X Page Buffer X X Program OTP Program Block Erase X X Full Chip Erase ...
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... Block Diagram F-A , F F-CE F-OE F-WE F-WP F -CE 1 -CE 2 -OE -WE -LB - F-V F 64M (x16) bit Flash memory 8M (x16) bit RAM - F-RY/ GND ...
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... Command Definitions for Flash Memory 5.1 Command Definitions Command Cycles Req’d Read Array Read Identifier Codes/OTP Read Query Read Status Register Clear Status Register Block Erase Full Chip Erase Program Page Buffer Program Block Erase and (Page Buffer) Program Suspend ...
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... Following the Clear Block Lock Bit command, block which is not locked-down is unlocked when F- When F- lock-down bit is disabled and the selected block is unlocked regardless of lock-down configuration. IH 11. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used ...
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... Identifier Codes and OTP Address for Read Operation Manufacturer Code Manufacturer Code Device Code 64M Bottom Parameter Device Code Block is Unlocked Block is Locked Block Lock Configuration Code Block is not Locked-Down Block is Locked-Down Device Configuration Code Partition Configuration Register OTP Lock ...
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... OTP Block Address Map ustomer Programmable Area Lock Bit (DQ Factory Programmed Area Lock Bit (DQ (1) 5.4 Functions of Block Lock and Block Lock-Down (2) State F- [000 ( [001] [011 [100 (4) [101] ( [110] [111 Notes: 1. OTP (One Time Program) block has the lock function which is different from those described above. ...
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... Block Locking State Transitions upon Command Write Current State DQ DQ State F-WP 1 [000 [001 [011 [100 [101 [110 [111 Notes: 1. “Set Lock” means Set Block Lock Bit command, “Clear Lock” means Clear Block Lock Bit command and “Set Lock- down” ...
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... Status Register Definition WSMS BESS BEFCES 7 6 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS (BESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR ...
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... SMS XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS Page Buffer Program available 0 = Page Buffer Program not available XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS ( Extended Status Register Definition ...
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... PCR.15-11 = RESERVED FOR FUTURE ENHANCEMENTS (R) PCR.10-8 = PARTITION CONFIGURATION (PC2-0) 000 = No partitioning. Dual Work is not allowed. 001 = Plane1-3 are merged into one partition. (default in a bottom parameter device) 010 = Plane 0-1 and Plane2-3 are merged into one partition respectively. ...
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... Memory Map for Flash Memory Bottom Parameter BLOCK NUMBER ADDRESS RANGE 134 32K-WORD 133 32K-WORD 132 32K-WORD 131 32K-WORD 130 32K-WORD 129 32K-WORD 128 32K-WORD 127 32K-WORD 12 32K-WORD 125 32K-WORD 124 32K-WORD 123 32K-WORD 122 32K-WORD 121 32K-WORD 120 32K-WORD ...
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... Absolute Maximum Ratings Symbol Parameter V Supply voltage CC V Input voltage IN T Operating temperature A T Storage temperature STG F-V F-V voltage PP PP Notes: 1. The maximum applicable voltage on any pins with respect to GND. 2. Except F -2.0V undershoot and V +2.0V overshoot are allowed when the pulse width is less than 20 nsec. ...
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... DC Electrical Characteristics Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO I F-V Standby Current CCS CC F-V Automatic Power Savings CC I CCAS Current I F-V Reset Power-Down Current CCD CC Average F-V CC Read Current Normal Mode I CCR Average F Word Read Read Current Page Mode ...
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... Symbol Parameter I S-V Standby Current S-V Standby Current SB1 CC I S-V Operation Current CC1 CC I S-V Operation Current CC2 CC V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH F-V Lockout during Normal PP V PPLK Operations F-V during Block Erase, Full Chip ...
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... AC Electrical Characteristics for Flash Memory 12.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load 12.2 Read Cycle Symbol t Read Cycle Time AVAV t Address to Output Delay AVQV t F-CE to Output Delay ELQV t Page Address Access Time ...
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... Write Cycle (F-WE / F-CE Controlled) Symbol t Write Cycle Time AVAV F-RST High Recovery to F-WE (F-CE) Going Low PHWL PHEL F-CE (F-WE) Setup to F-WE (F-CE) Going Low ELWL WLEL F-WE (F-CE) Pulse Width WLWH ELEH Data Setup to F-WE (F-CE) Going High DVWH DVEH Address Setup to F-WE (F-CE) Going High AVWH ...
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... Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance Symbol Parameter 4K-Word Parameter Block t WPB Program Time 32K-Word Main Block t WMB Program Time t / WHQV1 Word Program Time t EHQV1 t / WHOV1 OTP Program Time t EHOV1 t / 4K-Word Parameter Block WHQV2 ...
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... Flash Memory AC Characteristics Timing Chart AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code (A) 21 F-CE ( F-OE ( (W) F- High (D/Q) 15 (P) F-RST ...
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... AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks (A) 21 (A) 2 F-CE ( (G) F- (W) F- High (D/Q) 15 F-RST ( VALID ADDRESS AVQV VALID ...
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... AC Waveform for Write Operations(F-WE / F-CE Controlled ...
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... Reset Operations Symbol F-RST Low to Reset during Read t PLPH (F-RST should be low during power-up.) t F-RST Low to Reset during Erase or Program PLRH t F-V 2.7V to F-RST High VPH CC t F-V 2.7V to Output Delay VHQV CC Notes reset time required from the later of SR.7 (F-RY/BY) going “1” (High-Z) or F-RST going high until outputs PHQV are valid ...
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... AC Electrical Characteristics for SRAM 13.1 AC Test Conditions Input pulse level Input rise and fall time Input and Output timing Ref. level Output load Note: 1. Including scope and socket capacitance. 13.2 Read Cycle Symbol t Read Cycle Time RC t Address access time AA t Chip enable access time (S-CE ...
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... Write Cycle Symbol t Write cycle time WC t Chip enable to end of write CW t Address valid to end of write AW t Byte select time BW t Address setup time AS t Write pulse width WP t Write recovery time WR t Input data setup time DW t Input data hold time ...
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... SRAM AC Characteristics Timing Chart Read Cycle Timing Chart Standby IH Address S- High - Z DQ OUT Device Address Selection Address Stable LZ1,2 t ACE1,2 t BLZ OLZ Data alid Data alid ...
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... Write Cycle Timing Chart (S-WE Controlled ...
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... Write Cycle Timing Chart (S-CE Controlled ...
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... Write Cycle Timing Chart (S-UB, S-LB Controlled ...
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... Data Retention Characteristics for SRAM Symbol Parameter V Data Retention Supply voltage CCDR I Data Retention Supply current CCDR t Chip enable setup time CDR t Chip enable hold time R Notes 1. Reference value 25°C, S S-CE S-V - 0.2V, S- Data Retention timing chart (S-CE Controlled 2.7V 2.2V V CCDR ...
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... Notes This product is a stacked CSP package that a 64M (x16) bit Flash Memory and a 8M (x16) bit SRAM are assembled into. - Supply Power Maximum difference (between F-V - Power Supply and Chip Enable of Flash Memory and SRAM (F-CE, S-CE S-CE should not be “low” and S-CE ...
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... Flash Memory Data Protection Noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. Such noises, when induced onto F-WE signal or power supply, may be interpreted as false commands and causes undesired memory updating. To protect the data stored in the flash memory against unwanted writing, systems operating with the flash memory should have the following write protect designs, as appropriate: The below describes data protection method ...
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... Related Document Information Document No. FUM00701 Note: 1. International customers should contact their local SHARP or distribution sales offices and GND and between its F-V CC Power Supply trace. Use similar trace widths and layout considerations given to the F- PP voltage (See Chapter 11 ...
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... A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. For the AC specifications Memory” described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page ...
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... A-1.1.1 Rise and Fall Time Symbol t F-V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Parameter Notes Min ...
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... A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) Acceptable Glitch Noises See the “DC Electrical Characteristics” described in specifications for V (Min.) or above V (Max ...
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... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...
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... Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED event will SHARP be liable any way responsible, for any incidental or consequential economic or property damage. ...