MT54W512H36JF-6 Micron Semiconductor Products, MT54W512H36JF-6 Datasheet

MT54W512H36JF-6

Manufacturer Part Number

MT54W512H36JF-6

Description

512K x 36 1.8V VDD, HSTL, QDRIIb4 SRAM

Manufacturer

Micron Semiconductor Products

Datasheet

1.MT54W512H36JF-6.pdf (24 pages)

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18Mb QDR™II SRAM

4-Word Burst

FEATURES

• 18Mb Density (2 Meg x 8, 1 Meg x 18, 512K x 36)

• DLL circuitry for wide-output, data valid window

• Separate independent read and write data ports with

• 100% bus utilization DDR READ and WRITE

• Fast clock to valid data times

• Full data coherency, providing most current data

• Four-tick burst for reduced-address frequency

• Double data rate operation on read and write ports

• Two input clocks (K and K#) for precise DDR timing

• Two output clocks (C and C#) for precise flight time

• Single address bus

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• +1.8V core and HSTL I/O

• Clock-stop capability with s restart

• 13x15mm, 1mm pitch, 11 x 15 grid FBGA package

• User programmable impedance output

• JTAG boundary scan

OPTIONS

• Clock Cycle Timing

• Configurations

• Package

VALID PART NUMBERS

18Mb 1.8V V

MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

‡

PART NUMBER

MT54W2MH8JF-xx

MT54W1MH18JF-xx

MT54W512H36JF-xx

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

and future frequency scaling

concurrent transactions

operation

at clock rising edges only

and clock skew matching—clock and data delivered

together to receiving device

3ns (333 MHz)

3.3ns (300 MHz)

4ns (250 MHz)

5ns (200MHz)

6ns (167 MHz)

7.5ns (133 MHz)

165-ball, 13mm x 15mm FBGA

2 Meg x 8

1 Meg x 18

512K x 36

, HSTL, QDRIIb4 SRAM

DESCRIPTION

2 Meg x 8, QDRIIb4 FBGA

1 Meg x 18, QDRIIb4 FBGA

512K x 36, QDRIIb4 FBGA

MT54W512H36J

MT54W1MH18J

MARKING

MT54W2MH8J

-3.3

-7.5

-3

-4

-5

-6

2 MEG x 8, 1 MEG x 18, 512K x 36

MT54W2MH8J

MT54W1MH18J

MT54W512H36J

GENERAL DESCRIPTION

nous, pipelined, burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS pro-

cess. The QDR architecture consists of two separate DDR

(double data rate) ports to access the memory array. The

read port has dedicated data outputs to support READ

operations. The write port has dedicated data inputs to

support WRITE operations. This architecture eliminates

the need for high-speed bus turnaround. Access to each

port is accomplished using a common address bus. Ad-

dresses for reads and writes are latched on rising edges of

the K and K# input clocks, respectively. Each address

location is associated with four data words that burst

sequentially into or out of the device. Since data can be

transferred into and out of the device on every rising edge

of both clocks (K, K#, C and C#), memory bandwidth is

maximized while simplifying system design by eliminat-

ing bus turnarounds.

for each port (read R#, write W#) which are received at K

rising edge. Port selects permit independent port opera-

tion. All synchronous inputs pass through registers con-

trolled by the K or K# input clock rising edges. Active LOW

byte writes (BWx#) permit byte or nybble write selection.

Write data and byte writes are registered on the rising

edges of both K and K#. The addressing within each burst

1.8V V

The Micron

Depth expansion is accomplished with port selects

QDR™II (Quad Data Rate™) synchro-

165-BALL FBGA

, HSTL, QDRIIb4 SRAM

ADVANCE

‡

Related parts for MT54W512H36JF-6

MT54W512H36JF-6 Summary of contents

Page 1

... VALID PART NUMBERS PART NUMBER DESCRIPTION MT54W2MH8JF-xx 2 Meg x 8, QDRIIb4 FBGA MT54W1MH18JF-xx 1 Meg x 18, QDRIIb4 FBGA MT54W512H36JF-xx 512K x 36, QDRIIb4 FBGA 18Mb 1. HSTL, QDRIIb4 SRAM DD MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’ ...

Page 2

GENERAL DESCRIPTION (continued) of four is fixed and sequential, beginning with the lowest address and ending with the highest one. All synchro- nous data outputs pass through output registers con- trolled by the rising edges of the output clocks (C ...

Page 3

PROGRAMMABLE IMPEDANCE OUTPUT BUFFER The QDR SRAM is equipped with programmable im- pedance output buffers. This allows a user to match the driver impedance to the system. To adjust the imped- ance, an external precision resistor (RQ) is connected between ...

Page 4

MEG x 8 PIN ASSIGNMENT (TOP VIEW CQ# V /SA ...

Page 5

MEG x 18 PIN ASSIGNMENT (TOP VIEW CQ# V /SA* NC/SA D10 D NC D11 Q10 Q11 F NC Q12 D12 G NC D13 ...

Page 6

PIN ASSIGNMENT (TOP VIEW CQ# V /SA* NC/SA Q27 Q18 D18 C D27 Q28 D19 D D28 D20 Q19 E Q29 D29 Q20 F Q30 Q21 D21 G D30 D22 Q22 ...

Page 7

FBGA BALL DESCRIPTIONS BALL SYMBOL TYPE 7C, 8B, 5C, 4B, SA Input 9R, 8P, 8R, 7R, 7N, 7P, 6N, 5R, 5N, 5P, 4P, 4R, 3R, 9A, 3A, 10A Input 4A W# Input 7B BW_# Input 7A NW_# ...

Page 8

FBGA BALL DESCRIPTIONS (continued) BALL SYMBOL TYPE 1H DLL# Input 10P, 11N, 11M, D_ Input 10K, 11J, 11G, 10E, 11D, 11C, 10N, 9M, 9L, 9J, 10G, 9F, 10D, 9C, 9B, 3B, 3C, 2D, 3F, 2G, 3J, 3L, 3M, 2N, 1C, ...

Page 9

RD & R_Count=4 LOAD NEW READ ADDRESS; R_Count=0; always R_Init=1 WT & W_Count=4 LOAD NEW WRITE ADDRESS; W_Count=0 always NOTE: 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation. The address order is always fixed ...

Page 10

TRUTH TABLE (Notes 1–8) OPERATION WRITE Cycle: Load address, input write data on 2 consecutive K and K# rising edges READ Cycle: Load address, output data on 2 consecutive C and C# rising edges NOP: No operation STANDBY: Clock stopped ...

Page 11

ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V ........................................ -0.5V to +2.9V SS Voltage Supply DD Relative to V ........................................... -0. .......................................................... -0. Storage Temperature .............................. -55ºC ...

Page 12

I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (+20ºC T +110º MAX unless otherwise noted DESCRIPTION CONDITIONS Operating All inputs V t Supply Current: Cycle time KHKH (MIN); I DDR Outputs open t t Standby Supply KHKH ...

Page 13

AC ELECTRICAL CHARACTERISTICS (Notes 1–5, 7, 8); (+20ºC T +110ºC; +1.7V J DESCRIPTION Clock Average clock cycle time (K, K#, C, C#) Clock Phase Jitter (K, K#, C, C#) Clock HIGH time (K, K#, C, C#) Clock LOW time (K, ...

Page 14

AC TEST CONDITIONS Input pulse levels ................................. 0.25V to 1.25V Input rise and fall times ...................................... 0.3ns Input timing reference levels ............................ 0.75V Output reference levels .................................. V ZQ for 50 impedance ....................................... 250 Output load .............................................. See Figure 1 ...

Page 15

NOP READ KHKL t KLKH t KHKH IVKH AVKH t KHAX D Qx2 Qx3 Q t KHCH C t KHCH C# CQ CQ# NOTE: 1. Q00 refers to output ...

Page 16

IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The QDR SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990, but does not have the set of functions required for full 1149.1 compliance. ...

Page 17

TEST DATA-OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 2.) The output changes on the falling edge ...

Page 18

The TAP controller does recognize an all-0 instruc- tion. When an EXTEST instruction is loaded into the instruction register, the SRAM responds SAMPLE/ PRELOAD instruction has been loaded. EXTEST does not place the SRAM outputs in a ...

Page 19

Test Clock (TCK) Test Mode Select (TMS) Test Data-In (TDI) Test Data-Out (TDO) TAP AC ELECTRICAL CHARACTERISTICS (Notes 1, 2) (+20ºC T +100ºC, +1.7V J DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times ...

Page 20

TAP AC TEST CONDITIONS Input pulse levels ...................................... V Input rise and fall times ....................................... 1ns Input timing reference levels ............................. 0.9V Output reference levels ...................................... 0.9V Test load termination supply voltage ................ 0.9V TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING ...

Page 21

IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD ALL DEVICES REVISION NUMBER (31:29) DEVICE ID 00def0wx0t0q0b0s0 (28:12) MICRON JEDEC ID 00000101100 CODE (11:1) ID Register Presence Indicator (0) SCAN REGISTER SIZES REGISTER NAME BIT SIZE (x18) Instruction 3 Bypass Boundary ...

Page 22

BIT# FBGA BALL 11P 11 10P 12 10N 10M 15 11N 11L 19 ...

Page 23

BALL A11 165X Ø 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø 0.40 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. ...

Page 24

REVISION HISTORY Rev. 2, Pub. 11/01, ADVANCE ................................................................................................................................. 11/01 • Changed AC timing 18Mb 1. HSTL, QDRIIb4 SRAM DD MT54W1MH18J_3.p65 – Rev. 3, Pub. 12/01 2 MEG MEG x 18, 512K x 36 1.8V V ...

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