LH28F160S3B-L10A Sharp, LH28F160S3B-L10A Datasheet
LH28F160S3B-L10A
Related parts for LH28F160S3B-L10A
LH28F160S3B-L10A Summary of contents
Page 1
... Flash Memory LH28F160S3B-L10A Date Mar. 23. 2001 ...
Page 2
Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. When using the products covered herein, please observe ...
Page 3
INTRODUCTION ...................................................... 3 1.1 Product Overview ................................................ 3 2 PRINCIPLES OF OPERATION ................................ 6 2.1 Data Protection ................................................... 7 3 BUS OPERATION.................................................... 7 3.1 Read ................................................................... 7 3.2 Output Disable .................................................... 7 3.3 Standby ............................................................... 7 3.4 Deep Power-Down ...
Page 4
... GND, selective hardware block locking, or flexible software block locking. These alternatives give designers ultimate control of their code security needs. The LH28F160S3B-L10A is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface (CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer rates and minimize device and system-level implementation costs. The LH28F160S3B-L10A is manufactured on SHARP’ ...
Page 5
... LH28F160S3B-L10A specifications. Section 1 provides a flash memory overview. Sections and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Product Overview The LH28F160S3B-L10A is a high-performance 16M- bit Smart 3 Flash memory 2MBx8/1MBx16. The 2MB of data is arranged in thirty-two 64K-byte blocks which are individually erasable, lockable, and unlockable in-system ...
Page 6
Output Buffer Y Input Decoder Buffer Address X Decoder Latch Address Counter Figure 1. Block Diagram WP WE# 18 ...
Page 7
Symbol Type ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are internally latched during a write cycle Byte Select Address. Not used in x16 mode(can be floated INPUT ...
Page 8
... PRINCIPLES OF OPERATION The LH28F160S3B-L10A Flash memory includes an on-chip WSM to manage block erase, full chip erase, (multi) word/byte write and configuration functions. It allows for: 100% TTL-level control inputs, fixed power supplies during block erase, full chip erase, (multi) word/byte write and block lock-bit configuration, and minimal processor overhead with RAM-Like interface timings ...
Page 9
... If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. SHARP’s flash memories allow proper CPU initialization following a system reset through the use of the RP# input ...
Page 10
Read Identifier Codes Operation The read identifier codes operation outputs the manufacturer code, device code, block status codes for each block (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with ...
Page 11
Mode Notes RP# Read 1,2,3,9 V Output Disable 3 V Standby 3 V Deep Power-Down 4 V Read Identifier 9 V Codes Query 9 V Write 3,7,8,9 V Mode Notes RP# Read 1,2,3,9 V Output Disable 3 V Standby 3 ...
Page 12
... Following the Third Bus Cycle, inputs the write address and write data of ’N’ times. Finally, input the confirm command ’D0H’. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. LHF16KAN Table 4 ...
Page 13
Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until ...
Page 14
Query Command Query database can be read by writing Query command (98H). Following the command write, read cycle from address shown in Table 7~11 retrieve the critical information to write, erase and otherwise control the flash component ...
Page 15
CFI Query Identification String The Identification String provides verification that the component supports the Common Flash Interface specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are) supported. Offset Length (Word Address) 10H,11H,12H 03H ...
Page 16
Device Geometry Definition This field provides critical details of the flash device geometry. Offset Length (Word Address) 27H 01H 28H,29H 02H 2AH,2BH 02H 2CH 01H 2DH,2EH 02H 2FH,30H 02H 4.5.5 SCS OEM Specific Extended Query Table Certain flash features ...
Page 17
Block Erase Command Block erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence appropriate sequencing and an address ...
Page 18
... XSR.7. The Multi Word/Byte Write command can be queued while WSM is busy as long as XSR.7 indicates "1", because LH28F160S3B-L10A has two buffers error occurs while writing, the device will stop writing and flush next multi word/byte write command loaded in multi word/byte write command. Status register bit SR.4 will be set to " ...
Page 19
Block Erase Suspend Command The Block Erase Suspend command allows block- erase interruption to read or (multi) word/byte-write data in another block of memory. Once the block- erase process starts, writing the Block Erase Suspend command requests that the ...
Page 20
Set Block Lock-Bit Command A flexible block locking and unlocking scheme is enabled via block lock-bits. The block lock-bits gate program and erase operations With WP#=V individual block lock-bits can be set using the Set Block Lock-Bit command. See ...
Page 21
STS Configuration Command The Status (STS) pin can be configured to different states using the STS Configuration command. Once the STS pin has been configured, it remains in that configuration until another configuration command is issued, the device is ...
Page 22
WSMS BESS ECBLBS SR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy SR.6 = BLOCK ERASE SUSPEND STATUS 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE AND CLEAR ...
Page 23
Start Write 70H Read Status Register 0 SR.7= 1 Write 20H, Block Address Write D0H, Block Address Read Status Register Suspend Block No Erase Loop 0 Suspend SR.7= Block Erase Yes 1 Full Status Check if Desired Block Erase Complete ...
Page 24
Start Write 70H Read Status Register 0 SR.7= 1 Write 30H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Full Chip Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V ...
Page 25
Start Write 70H Read Status Register 0 SR.7= 1 Write 40H or 10H, Address Write Word/Byte Data and Address Read Status Register Suspend Word/Byte No Suspend 0 SR.7= Word/Byte Yes Write 1 Full Status Check if Desired Word/byte Write Complete ...
Page 26
Start Write E8H, Start Address Read Extend Status Register No 0 Yes Write Buffer XSR.7= Time Out 1 Write Word or Byte Count (N)-1, Start Address Write Buffer Data, Start Address X=1 Yes Yes Abort Buffer ...
Page 27
FULL STATUS CHECK PROCEDURE FOR MULTI WORD/BYTE WRITE OPERATION Read Status Register 1 SR.3= V Range Error SR.1= Device Protect Error 0 1 Command Sequence SR.4,5= Error 0 1 Multi Word/Byte Write SR.4= Error 0 Multi Word/Byte ...
Page 28
Start Write B0H Read Status Register 0 SR. Block Erase Completed SR.6= 1 (Multi) Word/Byte Write Read Read or Write ? Read Array Data (Multi) Word/Byte Write Loop No Done? Yes Write FFH Write D0H Block Erase Resumed ...
Page 29
Start Write B0H Read Status Register 0 SR. (Multi) Word/Byte Write SR.2= Completed 1 Write FFH Read Array Data Done No Reading Yes Write D0H Write FFH (Multi) Word/Byte Write Read Array Data Resumed Figure 11. (Multi) Word/Byte ...
Page 30
Start Write 60H, Block Address Write 01H, Block Address Read Status Register 0 SR.7= 1 Full Status Check if Desired Set Block Lock-Bit Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error PP 0 ...
Page 31
Start Write 60H Write D0H Read Status Register 0 SR.7= 1 Full Status Check if Desired Clear Block Lock-Bits Complete FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) 1 SR.3= V Range Error SR.1= Device Protect ...
Page 32
... DESIGN CONSIDERATIONS 5.1 Three-Line Output Control The device will often be used in large memory arrays. SHARP provides three control accommodate multiple memory connections. Three- Line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable CE# while OE# should be connected to all memory devices and the system’ ...
Page 33
RP# Transitions CC PP Block erase, full chip erase, (multi) word/byte write and block lock-bit configuration are not guaranteed if V falls outside of a valid V PP PPH1/2/3 outside of a valid V range, ...
Page 34
ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase, Write and Block Lock-Bit Configuration ........0°C to +70°C Temperature under Bias............... -10°C to +80°C Storage Temperature........................ -65°C to +125°C Voltage On Any Pin (except )............... ...
Page 35
AC INPUT/OUTPUT TEST CONDITIONS 2.7 INPUT 0.0 AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0." Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% ...
Page 36
DC CHARACTERISTICS Sym. Parameter I Input Load Current LI I Output Leakage Current Standby Current CCS Deep Power-Down CCD CC Current I V Read Current CCR Write Current CCW CC ...
Page 37
Sym. Parameter V Input Low Voltage IL V Input High Voltage IH V Output Low Voltage OL V Output High Voltage OH1 (TTL) V Output High Voltage OH2 (CMOS Lockout Voltage during PPLK PP Normal Operations V V ...
Page 38
AC CHARACTERISTICS - READ-ONLY OPERATIONS Versions Sym. Parameter t Read Cycle Time AVAV t Address to Output Delay AVQV t CE# to Output Delay ELQV t RP# High to Output Delay PHQV t OE# to Output Delay GLQV t ...
Page 39
Standby Address Selection V IH ADDRESSES( CE#( OE#( WE#( HIGH Z DATA(D/ PHQV V IH RP#( NOTE: ...
Page 40
Standby Address Selection V IH ADDRESSES( CE#( OE#( BYTE#( HIGH Z DATA(D/Q) (DQ - HIGH Z DATA(D/Q) ...
Page 41
AC CHARACTERISTICS - WRITE OPERATIONS Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V Setup ...
Page 42
Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to WE# Going Low PHWL t CE# Setup to WE# Going Low ELWL t WE# Pulse Width WLWH t WP# V Setup to WE# Going High SHWH IH ...
Page 43
V IH ADDRESSES( CE#( ELWL V IH OE#( WE#( High Z DATA(D/ BYTE#( High Z STS( ...
Page 44
ALTERNATIVE CE#-CONTROLLED WRITES Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup to CE# ...
Page 45
Versions Sym. Parameter t Write Cycle Time AVAV t RP# High Recovery to CE# Going Low PHEL t WE# Setup to CE# Going Low WLEL t CE# Pulse Width ELEH t WP# V Setup to CE# Going High SHEH IH ...
Page 46
V IH ADDRESSES( CE#( OE#( WE#( High Z DATA(D/ BYTE#( High Z STS( ...
Page 47
RESET OPERATIONS High Z STS( RP#( High Z STS( RP#( 2.7/3. RP#( Figure 21. AC Waveform for Reset Operation ...
Page 48
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE AND BLOCK LOCK-BIT CONFIGURATION PERFORMANCE Sym. Parameter Word/Byte Write Time t WHQV1 (using W/B write, in word t EHQV1 mode) Word/Byte Write Time t WHQV1 (using W/B write, in byte t ...
Page 49
Sym. Parameter t Word/Byte Write Time WHQV1 t (using W/B write, in word mode) EHQV1 t Word/Byte Write Time WHQV1 t (using W/B write, in byte mode) EHQV1 Word/Byte Write Time (using multi word/byte write) Block Write Time (using W/B ...
Page 50
... Device Density 160 = 16-Mbit Architecture S = Regular Block Power Supply Type 3 = Smart 3 Technology Operating Temperature Blank = 0°C ~ +70° -40°C ~ +85°C Option Order Code 1 LH28F160S3B-L10A LHF16KAN - Access Speed (ns) 10:100ns (3.3V), 120ns (2.7V) 13:130ns (3.3V), 150ns (2.7V) Package T = 56-Lead TSOP R = 56-Lead TSOP(Reverse Bend) ...
Page 51
Flash memory LHFXXKXX family Data Protection Noises having a level exceeding the limit specified in this document may be generated under specific operating conditions on some systems. Such noises, when induced onto WE# signal or power supply, may be interpreted ...
Page 52
A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate ...
Page 53
A-1.1.1 Rise and Fall Time Symbol t V Rise Time Input Signal Rise Time R t Input Signal Fall Time F NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device ...
Page 54
A-1.2 Glitch Noises Do not input the glitch noises which are below V as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal V (Min (Max.) IL Input Signal (a) ...
Page 55
... A-2 RELATED DOCUMENT INFORMATION Document No. AP-001-SD-E AP-006-PT-E AP-007-SW-E NOTE: 1. International customers should contact their local SHARP or distribution sales office. (1) Document Name Flash Memory Family Software Drivers Data Protection Method of SHARP Flash Memory RP#, V Electric Potential Switching Circuit PP iv Rev. 1.10 ...