RM7000B-500T PMC-Sierra Inc, RM7000B-500T Datasheet
RM7000B-500T
Specifications of RM7000B-500T
Related parts for RM7000B-500T
RM7000B-500T Summary of contents
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... Microprocessor with On-Chip Secondary Cache Proprietary and Confidential Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet RM7000B™ Data Sheet Preliminary Issue 3, March 2002 Preliminary ...
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... PMC-Sierra, Inc. has been advised of the possibility of such damage. Trademarks RM7000B and Fast Packet Cache are trademarks of PMC-Sierra, Inc. Patents The technology discussed is protected by one or more of the following Patents. U.S. Patent Numbers 5 953 748, 5 606 683, 5 760 620 Relevant patent applications and other patents may also exist ...
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... March 2001 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Details of Change Updated mode bit 11 description, table 16, Section 4.39. Updated Dhrystone value to 900, Section 1. Added Section 12, Thermal Information. ...
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... All bit and field names described in the text, such as Interrupt Mask, are in an italic-bold typeface. • All instruction names, such as MFHI, are in san serif typeface. Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 4 ...
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... Cache Locking .............................................................................................................19 4.23 Cache Management .....................................................................................................20 4.24 Primary Write Buffer .....................................................................................................20 4.25 System Interface ..........................................................................................................20 4.26 System Address/Data Bus ...........................................................................................21 4.27 System Command Bus ................................................................................................21 4.28 Handshake Signals ......................................................................................................22 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary ...
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... Clock Timing ................................................................................................................42 11.2 System Interface Timing ..............................................................................................42 12 Thermal Information ............................................................................................................. 43 13 Packaging Information .......................................................................................................... 44 14 RM7000B Pinout .................................................................................................................. 45 15 Ordering Information ............................................................................................................ 48 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary ...
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... Figure 11 Multiple Outstanding Reads ......................................................................................24 Figure 12 Clock Timing ..............................................................................................................42 Figure 13 Input Timing ...............................................................................................................42 Figure 14 Output Timing ............................................................................................................42 Figure 15 304 TBGA Drawing ...................................................................................................44 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary ...
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... Table 20 Interrupt Interface .......................................................................................................35 Table 21 JTAG Interface ...........................................................................................................35 Table 22 Initialization Interface ..................................................................................................35 Table 23 (VCCIO = 3.15V – 3.45V) ...........................................................................................38 Table 24 (VCCIO = 2.3V – 2.7V) ...............................................................................................38 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary ...
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... Fully static CMOS design with dynamic power down logic • Pin compatible with the RM5271, RM7000 and RM7000A in 304-pin TBGA package, 31x31mm Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary 2 ...
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... Cvt, Div, Sqrt Multiplier Array Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Extenal Cache Controller On-chip 256K Byte Secondary Cache, 4-way Set Associative Secondary Tags ...
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... It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit. The RM7000B integrates 16 KB 4-way set associative instruction and data caches along with an integrated 256 KB 4-way set associative secondary. The primary data and secondary caches are write-back and non-blocking ...
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... Superscalar Dispatch The RM7000B incorporates a superscalar dispatch unit that allows it to issue up to two instructions per cycle. For purposes of instruction issue, the RM7000B defines four classes of instructions: integer, load/store, branches, and floating-point. There are two logical pipelines, the function pipeline and the memory pipeline. Note however that the M pipe can execute integer as well as memory type instructions ...
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... Figure 4 shows instruction execution within the RM7000B when instructions are issuing simultaneously down both pipelines. As illustrated in the figure ten instructions can be executing simultaneously. This figure presents a somewhat simplistic view of the processors operation since the out-of-order completion of loads, stores, and long latency floating-point operations can result in there being even more instructions in process than what is shown ...
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... Register File The RM7000B has thirty-two general purpose registers with register location 0 (r0) hard wired to a zero value. These registers are used for scalar integer operations and address calculation. In order to service the two integer execution units, the register file has four read ports and two write ports and is fully bypassed both within and between the two execution units to minimize operation latency in the pipeline ...
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... ALU The RM7000B has two complete integer ALUs each consisting of an integer adder/subtractor, a logic unit, and a shifter. Table 3 shows the functions performed by the ALUs for each execution unit. Each of these units is optimized to perform all operations in a single processor cycle. Table 3 ALU Operations ...
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... RM7000B allow floating-point computation instructions to issue concurrently with integer instructions. 4.8 Floating-Point Unit The RM7000B floating-point execution unit supports single and double precision arithmetic, as specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root unit and a pipelined multiply/add unit. Overlap of divide/square root and multiply/add is supported. ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Repeat Rate single/double 4 ...
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... To support the non-blocking caches and enhanced interrupt handling capabilities of the RM7000B, both the data and control register spaces of CP0 are supported. In the data register space, which is accessed using the same registers as found in previous RM7000 processors. In the control space, which is accessed by the previously unused registers ...
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... These modes allow system software to provide a secure environment for user processes. Bits in the CP0 Status register determine which virtual addressing mode is used. In user mode, the RM7000B provides a single, uniform virtual address space of 256 32-bit mode). When operating in the kernel mode, four distinct virtual address spaces, totalling 1024 32-bit mode), are simultaneously available and are differentiated by the high-order bits of the virtual address ...
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... TLB entry. The second mechanism controls the replacement algorithm when a TLB miss occurs. The RM7000B provides a random replacement algorithm to select a TLB entry to be written with a new mapping. However, the processor also provides a mechanism whereby a system specific number of mappings can be locked into the TLB, thereby avoiding random replacement. This mechanism uses the CP0 Wired register and allows the operating system to guarantee that certain Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ ...
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... Note that both of the write-through protocols bypass both the secondary and the tertiary caches since neither of these caches support writes of less than a complete cache line. These protocols are used for both code and data on the RM7000B with data using write-back or write-through depending on the application. The write-through modes support the same efficient frame buffer handling as the RM5200 Family ...
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... The RM7000B supports cache locking on a per line basis. The contents of each line of the cache can be locked by setting a bit in the Tag RAM. Locking the line prevents its contents from being overwritten by a subsequent cache miss ...
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... If the tag matches, then the data is written into the data cache in the next cycle that the data cache is not accessed (the next non-load cycle). The store buffer allows the RM7000B to execute a store every processor cycle and to perform back-to-back stores without penalty. In the event of a store immediately followed by a load to the same address, a combined merge and cache write occurs such that no penalty is incurred ...
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... The RM7000B allows entries to be stored in the primary caches that do not necessarily have a corresponding entry in the secondary; the RM7000B does not force the primaries subset of the secondary. For example, if primary cache line A is being filled and a cache line already exists in the secondary for primary cache line B at the location where primary A’ ...
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... Tertiary Cache The RM7000B has direct support for an external tertiary cache. The tertiary cache is direct mapped and block write-through with byte parity protection for data. The RM7000B tertiary cache operates identical to the secondary cache of the RM527x while supporting additional size increments to support 4 MB and 8 MB caches. ...
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... Cache Locking The RM7000B allows critical code or data fragments to be locked into the primary and secondary caches. The user has complete control over the locking function. For instruction and data fragments in the primary caches, locking is accomplished by setting either or both of the cache lock enable bits and specifying the set in the CP0 ECC register, then executing either a load instruction for data Fill_I cache operation for instructions ...
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... RM7000B significantly improves the speed of operation of certain critical cache management operations. In particular, the speed of the Hit-Writeback-Invalidate and Hit- Invalidate cache operations has been improved, in some cases by an order of magnitude, over that of other MIPS processors. For example, Table 8 compares the RM7000B with the R4000 processor. Table 8 Penalty Cycles ...
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... System Address/Data Bus The 64-bit System Address Data (SysAD) bus is used to transfer addresses and data between the RM7000B and the rest of the system protected with an 8-bit parity check bus, SysADC[7:0]. The system interface is configurable to allow easy interfacing to memory and I/O systems of varying frequencies ...
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... Handshake Signals There are ten handshake signals on the system interface. Two of these, RdRdy* and WrRdy*, are driven by an external agent to indicate to the RM7000B whether it can accept a new read or write transaction. The RM7000B samples these signals before deasserting the address on read and write requests. ...
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... For processor reads, the RM7000B asserts ValidOut* and simultaneously drives the address and read command on the SysAD and SysCmd buses. If the system interface has RdRdy* asserted, then the processor tristates its drivers and releases the system interface to slave state by asserting Release*. The external agent can then begin sending data to the RM7000B. ...
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... PRqst* PAck* TcMatch 4.30 Data Prefetch The RM7000B supports the MIPS IV integer data prefetch ( prefetch ( PREFX ) instructions. These instructions are used by the compiler assembly language programmer when it is known or suspected that an upcoming data reference is going to miss in the cache. By appropriately placing a prefetch instruction, the memory latency can be hidden under the execution of other instructions ...
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... WrRdy*. 4.32 External Requests The RM7000B can respond to certain requests issued by an external agent. These requests take one of two forms: Write requests and Null requests. An external agent executes a write request when it wishes to update one of the processors writable resources such as the internal interrupt register ...
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... Performance Counters To facilitate system tuning, the RM7000B implements a performance counter using two new CP0 registers, PerfCount and PerfControl. The PerfCount register is a 32-bit writable counter which causes an interrupt when bit 31 is set. The PerfControl register is a 32-bit register containing a 5-bit field which selects one of twenty-two event types as well as a handful of bits which control the overall counting function ...
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... IE=1, and the Interrupt Mask bit 13 (IM13) of the coprocessor 0 interrupt control register is set. Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Clock cycles Total instructions issued ...
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... Interrupt Handling In order to provide better real time interrupt handling, the RM7000B provides an extended set of hardware interrupts, each of which can be separately prioritized and separately vectored. In addition to the standard six external interrupt pins, the RM7000B provides four more interrupt pins for a total of ten external interrupts ...
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... Table 13 and Table 14 above. The priority level registers are located in the coprocessor 0 control register space. In addition to programmable priority levels, the RM7000B also permits the spacing between interrupt vectors to be programmed. For example, the minimum spacing between two adjacent vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set up the vectors as jumps to the actual interrupt service routines or, if interrupt latency is not paramount, to include the entire interrupt service routine at one vector ...
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... Standby Mode The RM7000B provides a means to reduce the amount of power consumed by the internal core when the CPU is not performing any useful operations. This state is known as Standby Mode. Executing the instruction enables interrupts and causes the processor to enter Standby WAIT Mode ...
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... Dual-cycle deselect (DCD) 1: Single-cycle deselect (SCD) Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Mode bit Description 17:16 System configuration identifiers - software visible in processor Config[21:20] register ...
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... Input RdType Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Description External request Signals that the external agent is submitting an external request. Release interface Signals that the processor is releasing the system interface to slave ...
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... System command/data identifier bus A 9-bit bus for command and data identifier transmission between the processor and an external agent. System Command/Data Identifier Bus Parity For the RM7000B, unused on input and zero on output. Description System clock Master clock input used as the system interface reference clock. All output timings are relative to this input clock ...
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... Input/Output Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Tertiary Cache Line Index Tertiary Cache Tag Match This signal is asserted by the cache Tag RAMs when a match occurs between the value on its data inputs and the contents of the addressed location in the RAM ...
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... ROM When asserted, this signal indicates to the RM7000B that the V power supply has been above the recommended value for more than 100 milliseconds and will remain stable. The assertion of V initiates the reading of the boot-time mode control serial stream. ...
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... Not more than one output should be shorted at a time. Duration of the short should not exceed 30 seconds. Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet 1 Limits 2 – ...
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... CC 2. Applying a logic high state to any I/O pin before specified in IEEE 1149.1 (JTAG), the JTMS pin must be held high during reset to avoid entering JTAG test mode. Refer to the RM7000B Family Users Manual, Appendix must be connected Manual for recommended circuit. ...
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... Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Maximum Conditions 0 OUT 0 OUT 0 0 ±15 µ ± ...
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... I/O supply power is application dependant, but typically <20 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Conditions 2 Maximum with no FPU operation Maximum worst case instruction mix Int) with worst case temperature (maximum TCase) ...
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... JTAG Clock Period t JTAGCKP Note 1. Operation of the RM7000B is only guaranteed with the Phase Lock Loop Enabled. Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Min ...
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... Mode Data Setup t DS Mode Data Hold t DH Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet 5,6 mode14.. (fastest) 5,6 mode14.. (slowest see above table ...
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... SysCmd, ValidIn*, ValidOut*, etc.) Figure 13 Input Timing SysClock Data Figure 14 Output Timing SysClock Data Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet t t High Low t t Fall Rise t t ...
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... MHz; with V Int = 1.5 V, maximum long-term operating junction temperature = 90°C, and CC maximum junction temperature for short-term excursions = 90°C. Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet 2 1.3 4.6 4.2 W 3.8 W ...
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... All dimensions in millimeters unless otherwise indicated. Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet E1, N ...
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... CC J1 SysAD7 J2 J20 V IO J21 CC K1 SysAD40 K2 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Function Pin Function Not Connect ...
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... SysCmd1 AB15 TcClr* AB16 TcTDE* AB19 INT4* AB20 V Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Pin Function K22 SysAD55 L3 SysAD9 L22 SysAD22 M3 SysAD42 M22 ...
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... V lO AC13 SS AC16 V lO AC17 SS AC20 INT5* AC21 Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet Function Pin Function V IO AC2 V lnt CC SS WrRdy* AC6 V ...
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... Ordering Information RM7000B -123 T Valid Combinations RM7000B-450T RM7000B-500T Proprietary and Confidential to PMC-Sierra, Inc and for its Customers’ Internal Use Document ID: PMC-2010588, Issue 3 RM7000B™ Microprocessor with On-Chip Secondary Cache Data Sheet I Temperature Grade: (blank) = commercial I = Industrial Package Type TBGA Device Maximum Speed Device Type ...