LXT3108BE Intel Corporation, LXT3108BE Datasheet
LXT3108BE
Available stocks
Related parts for LXT3108BE
LXT3108BE Summary of contents
Page 1
Intel LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit ® The Intel LXT3108 is an octal 3.3 V Long Haul/Short Haul (LH/SH) T1/E1/J1 Line interface unit (LIU). This flexible LIU allows the design of T1/E1/J1 LH/SH multi-service cards ...
Page 2
... OverDrive, Paragon, PC Dads, PC Parents, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, ProShare, RemoteExpress, Screamline, Shiva, SmartDie, Solutions960, Sound Mark, StorageExpress, The Computer Inside, The Journey Inside, This Way In, TokenExpress, Trillium, Vivonic, and VTune are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
Page 3
Contents 1.0 Pin Assignments ......................................................................................................................... 11 2.0 Signal Descriptions ..................................................................................................................... 13 3.0 T1/E1/J1 Nomenclature ...............................................................................................................27 ® 4.0 Intel LXT3108 LIU Nomenclature .............................................................................................. 29 5.0 Functional Description................................................................................................................ 31 6.0 Port Descriptions......................................................................................................................... 33 7.0 Software Support......................................................................................................................... 37 8.0 Initialization ..................................................................................................................................39 8.1 CLAD ...
Page 4
Contents 13.1.2 Analog Loopback ................................................................................................... 55 13.1.3 Digital Loopback .................................................................................................... 56 13.1.4 Remote Loopback.................................................................................................. 56 13.1.5 Transmit All Ones (TAOS) ..................................................................................... 57 13.2 Line Coding......................................................................................................................... 58 13.2.1 Alternate Mark Inversion (AMI) .............................................................................. 58 13.2.1.1 Bipolar with Eight Zero Substitution (B8ZS)........................................... ...
Page 5
Figures ® 1 Intel LXT3108 LIU Block Diagram............................................................................................... 9 ® 2 Intel LXT3108 HE 208 Pin Assignment .................................................................................... 11 ® 3 Intel LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments ........................................12 4 T1/E1/J1 LIU Block Diagram ...................................................................................................... 31 ® ...
Page 6
Contents Tables 1 LXT3108 Pin Description ............................................................................................................ 13 2 CLAD Initialization Options ......................................................................................................... 39 3 Transformer Specifications for the Intel 4 Preset Pulse Shaping Settings and Conditions .......................................................................... 45 5 Transmit Return Loss Specifications for Frequency Range and Magnitude .............................. ...
Page 7
Electrical Characteristics (Over Recommended Operating Conditions) ..................................... Transmitter Analog Characteristics ....................................................................................... Receiver Analog Characteristics ........................................................................................... Transmitter Analog Characteristics ....................................................................................... Receiver Analog Characteristics ........................................................................................... 90 55 Master and ...
Page 8
Contents Revision History Date May 2002 Janyary 2002 July 2001 8 Revision Modified Figure 10, 32, 33, 34, 35 Modified Tables 11, 12, 13, 14, 15, 18, 23, 24, 25, 26, ...
Page 9
Figure 1. Intel LXT3108 LIU Block Diagram Datasheet REMOTE LOOPBACK DIGITAL LOOPBACK ANALOG LOOPBACK ® Intel LXT3108 LIU 9 ...
Page 10
Intel LXT3108 LIU This page intentionally left blank. 10 Datasheet ...
Page 11
Pin Assignments ® Figure 2. Intel LXT3108 HE 208 Pin Assignment VCCIO ..... 53 DVCC ..... 54 DVSS ..... 55 AVCC ..... 56 RRING0 ..... 57 RTIP0 ..... 58 AVSS ..... 59 TXVSS ..... 60 TXVCC ..... 61 TVSS ...
Page 12
Intel LXT3108 LIU ® Figure 3. Intel LXT3108 BE 256 Plastic Ball Grid Array (PBGA) Assignments TTIP7 VCCIO DVCC RRING7 TXVCC B RPOS7 RNEG7 VSS RTIP7 TRING7 C TPOS7 TNEG7 VSS VSS AVCC D ...
Page 13
Signal Descriptions Table 1. LXT3108 Pin Description (Sheet 1 of 13) QFP PBGA Symbol 1 A1 VCCIO RPOS7 RDATA7 RNEG7 RBPV7 4 D5 RCLK7 Datasheet Description I/O Bipolar Mode S Power (I/O). Receive Positive Data/Receive ...
Page 14
Intel LXT3108 LIU Table 1. LXT3108 Pin Description (Sheet 2 of 13) QFP PBGA Symbol TPOS7 TDATA7 6 C2 TNEG7 7 D4 TCLK7 RPOS6 RDATA6 14 Description I/O Bipolar Mode Transmit Positive Data/Transmit Data Input ...
Page 15
Table 1. LXT3108 Pin Description (Sheet 3 of 13) QFP PBGA Symbol I/O RNEG6 RBPV6 10 D2 RCLK6 DO TPOS6 TDATA6 12 E3 TNEG6 13 E1 TCLK6 RPOS5 RDATA5 RNEG5 ...
Page 16
Intel LXT3108 LIU Table 1. LXT3108 Pin Description (Sheet 4 of 13) QFP PBGA Symbol RNEG4 RBPV4 22 G2 RCLK4 TPOS4 TDATA4 24 H1 TNEG4 25 H3 TCLK4 26 H2 GNDIO 27 J1 VCCIO RPOS3/ ...
Page 17
Table 1. LXT3108 Pin Description (Sheet 5 of 13) QFP PBGA Symbol I/O RNEG2 RBPV2 36 L4 RCLK2 DO TPOS2 TDATA2 38 M1 TNEG2 39 L2 TCLK2 RPOS1 RDATA1 RNEG1 ...
Page 18
Intel LXT3108 LIU Table 1. LXT3108 Pin Description (Sheet 6 of 13) QFP PBGA Symbol RNEG0 RBPV0 48 N5 RCLK0 TPOS0 TDATA0 50 P2 TNEG0 51 P3 TCLK0 52 P4 GNDIO 53 R2 VCCIO 54 ...
Page 19
Table 1. LXT3108 Pin Description (Sheet 7 of 13) QFP PBGA Symbol I TVSS 66 T8 DVSS 67 T6 DVCC 68 N9 TVSS 69 R6 TTIP1 TRING1 AO 71 P10 TVSS 72 R4 TXVCC 73 ...
Page 20
Intel LXT3108 LIU Table 1. LXT3108 Pin Description (Sheet 8 of 13) QFP PBGA Symbol 95 M10 TVSS 96 T10 TXVCC 97 M7 TXVSS 98 M8 AVSS 99 R13 RTIP3 100 T14 RRING3 101 N11 AVCC 102 M6 DVSS ...
Page 21
Table 1. LXT3108 Pin Description (Sheet 9 of 13) QFP PBGA Symbol I/O 120 L15 TYPE2 121 K16 TYPE1 122 L14 CS 123 M13 MCLK 124 K15 GND 125 J16 GND 126 K14 VMOAT 127 J14 RBIAS 128 K13 QVSS ...
Page 22
Intel LXT3108 LIU Table 1. LXT3108 Pin Description (Sheet 10 of 13) QFP PBGA Symbol 139 H13 DB4 DI/O 140 F14 DB5 DI/O 141 F15 DB6 DI/O 142 E16 DB7 DI/O 143 G15 GNDIO 144 E14 VCCIO 145 E15 ...
Page 23
Table 1. LXT3108 Pin Description (Sheet 11 of 13) QFP PBGA Symbol I/O 161 A14 RRING4 162 B14 RTIP4 163 C13 AVSS 164 D11 TXVSS 165 A13 TXVCC 166 B13 TVSS 167 A12 TRING4 AO 168 A11 TTIP4 AO 169 ...
Page 24
Intel LXT3108 LIU Table 1. LXT3108 Pin Description (Sheet 12 of 13) QFP PBGA Symbol 191 B7 TRING6 192 A6 TTIP6 193 C4 TVSS 194 A2 DVCC 195 C5 DVSS 196 C6 TVSS 197 A5 TTIP7 198 B5 TRING7 ...
Page 25
Table 1. LXT3108 Pin Description (Sheet 13 of 13) QFP PBGA Symbol I/O T2 DVCC M9 D8, F5, F6, F7, F8, F9, F10, F11, F12, G5, G6, G7, G8, G9, G10, G11, G12, H5, H6, H7, H8, H9, H10, VSS ...
Page 26
Intel LXT3108 LIU This page intentionally left blank. 26 Datasheet ...
Page 27
T1/E1/J1 Nomenclature The nomenclature in this document follows telecommunication industry standard conventions, i.e., bit, channel, and frame numbering increase sequentially with time. In the case of bit ordering, unless otherwise stated, the Most Significant Bit (MSB) is transmitted first ...
Page 28
Intel LXT3108 LIU This page intentionally left blank. 28 Datasheet ...
Page 29
Intel LXT3108 LIU Nomenclature ® The Intel LXT3108 LIU is an octal device, meaning that it supports up to eight T1/E1/J1 ports. The ports are numbered sequentially, beginning with zero and ending with seven. A port is defined ...
Page 30
Intel LXT3108 LIU This page intentionally left blank. 30 Datasheet ...
Page 31
Functional Description Each port consists of a transmitter and a receiver with a jitter attenuator switched between each path. Access to the host device is via a microprocessor parallel interface configured in either Intel or Motorola* mode. JTAG built-in ...
Page 32
Intel LXT3108 LIU The programmer controls overall device operation of the Intel registers. Each individual LIU is separately controlled by a set of PPRs. There are eight sets of PPRs, one for each port also possible to ...
Page 33
Port Descriptions ® The Intel LXT3108 LIU is a port-by-port programmable, fully integrated eight-port LIU with jitter attenuator as well as network control and maintenance functions. Each Intel port is suitable for mixed LH or SH, T1/E1/J1 telecommunications applications ...
Page 34
Intel LXT3108 LIU ® The Intel LXT3108 LIU is fully T1/E1/J1 selectable without the need to change any external components for twisted pair applications, allowing the development of a single board design to support T1 and E1 designs. The ...
Page 35
Figure 7. Transmitter Circuit for Twisted Pair and Coaxial Cable TTIP TRING NOTE: 1. Actual values of R1 and C1 may vary depending on design. Trimming each port’s transmitter circuit components to a single transformer and a capacitor increases design ...
Page 36
Intel LXT3108 LIU This page intentionally left blank. 36 Datasheet ...
Page 37
Software Support ® The Intel LXT3108 LIU comes with a complete set of software support. The various software modules allow the user to: • Configure the device through a Graphical User Interface (GUI). The Intel GUI software allows you ...
Page 38
Intel LXT3108 LIU This page intentionally left blank. 38 Datasheet ...
Page 39
Initialization During power up, the Power-On-Reset (POR) circuit initiates a reset sequence after the power supply reaches threshold of approximately 60% of VCC. On crossing this threshold, the device begins a 32 msec reset cycle to calibrate internal phase ...
Page 40
Intel LXT3108 LIU This page intentionally left blank. 40 Datasheet ...
Page 41
Power Supply Requirements 9 Tolerant I/O Pins All digital input pins will tolerate 5.0 volts and are compatible with TTL logic. Please note that it is recommended to keep digital input pins less than 2 volts above ...
Page 42
Intel LXT3108 LIU — TVCC — AVCC — QVCC The recommended method is to connect all of the analog pins to a wide PCB trace, and connect one end of the PCB trace to the power plane. Bypass capacitors ...
Page 43
Transmitter Each of the eight ports’ transmitters offers several features when interfacing with the framer device’s port transmitter control signals at the line rate and TDATA or TPOS/TNEG carrying digital traffic, the line driver will output a T1/ E1/J1 ...
Page 44
Intel LXT3108 LIU 10.1 Transmit Line Interface Each of the eight transmitters has pre-programmed and preset pulse shapes suited for driving T1 and E1 twisted-pair cables applications. The signal from TTIP and TRING of each ...
Page 45
Transmit Impedance Termination ® The Intel LXT3108 LIU’s LIU transmitter will synthesize its output impedance to match either a 100 Ω, a 110 Ω 120 Ω line as set by the TXTERM bits in 05h” on page ...
Page 46
Intel LXT3108 LIU By appropriate software control of the internal transmit impedance in Register, 05h, the transmit return loss will be maximized. There are three standards that can be checked for minimum transmit return loss. For E1 line rate, ...
Page 47
Typically SH pulses use only bytes, although all 48 bytes are available. LH pulse shaping may extend up to three baud. ...
Page 48
Intel LXT3108 LIU 10.2.1 Transmit Idle Operation and Tri-stating Drivers When the transmitter is not being used, the designer conserves power by powering down the driver circuit. There are two ways to power down the transmitter: • Set bit ...
Page 49
Receiver The eight receivers in the Intel following paragraphs describe the operation of one receiver. The receiver is coupled to the line through a 1:1 transformer. The input common mode level is set on-chip. Recovered data is presented at ...
Page 50
Intel LXT3108 LIU 11.3 Receiver Line Interface ® The Intel LXT3108 LIU receiver line interface provides: • Programmable line termination described in page 75. • Programmable sensitivity described in • Monitor mode, also in ® The Intel LXT3108 LIU ...
Page 51
Table 7. Programming Receiver Sensitivity RXCON RX[4:0] hex 11.3.2.1 Receiver Monitor Mode The receive equalizer of ...
Page 52
Intel LXT3108 LIU page 75. Receiver Equalizer Status Two Page Register, 08h The contents of Receiver Equalizer Status Zero Page Register, One Page Register, 07h length. 52 can be used to estimate the line attenuation, which can be translated ...
Page 53
Jitter Attenuation (JA) A digital Jitter Attenuation Loop (JAL) combined with an Elastic Store (ES) FIFO provides Jitter attenuation. The FIFO depth is selectable for either bits, through Register, 1Dh” on page frequency (higher than line ...
Page 54
Intel LXT3108 LIU This page intentionally left blank. 54 Datasheet ...
Page 55
Network Control and Maintenance Functions 13.1 Diagnostic Modes ® The Intel LXT3108 LIU offers the following diagnostic modes: • Network Loop (NLOOP) Code Generator/Detector. • Analog loopback (ALOOP) digital transmitter to analog transmitter/receiver pins back to digital receiver pins. ...
Page 56
Intel LXT3108 LIU RRING) as shown in corresponding LIU. Note that signals on the RTIP & RRING pins are ignored during analog loopback. The ALOOP bit is Figure 16. Analog Loopback TCLK TPOS TNEG RCLK RPOS RNEG 13.1.3 Digital ...
Page 57
Figure 18. Remote Loopback TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 13.1.5 Transmit All Ones (TAOS) The TAOS mode is set by asserting the TAOS bit in that the TAOS generator uses MCLK as a timing reference. In ...
Page 58
Intel LXT3108 LIU Figure 20. TAOS with Digital Loopback MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled Figure 21. TAOS with Analog Loopback MCLK TAOS Mode TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 13.2 Line ...
Page 59
AMI is a Return-to-Zero (RZ) format where a binary “one” (mark) is represented by either a positive or negative going pulse and a binary “zero” (space) is represented by the absence of a ® pulse. The Intel LXT3108 LIU supports ...
Page 60
Intel LXT3108 LIU Receive side HDB3 decoding is selected by setting the decoding bit in Page Register, 1Ch. Similarly, transmit side HDB3 encoding is selected by setting the encoding bit in Line Coding Control One Page Register, are not ...
Page 61
Table 9. LOS Criteria for Intel Standard T1.231 T1 ITU I.431 E1 G.775 E1 ITU I.431 E1 ETSI 300 233 E1 long haul Table 10. LOS Register Configurations Reg addr: 01H (master) bit-4 bit-3 usr_los I431 ...
Page 62
Intel LXT3108 LIU required for receive operation.) When the LOS condition is cleared, the LOS flag is reset and another transition replaces MCLK with the recovered clock at RCLK. RPOS/RNEG will be high during the entire LOS detection period ...
Page 63
ANSI T1.231) T1 AIS (Blue Alarm) is declared when less than nine spaces (i.e less zeros) are detected in a 8192-bit wide window. When AIS is detected, the appropriate bit in the AIS status register is set ...
Page 64
Intel LXT3108 LIU 13.3.3.3 Excess Zeroes (EXZ) The definition of an EXZ depends upon the line coding format, as explained in Table 13. The line signal is monitored for any violations of the maximum space rule as set in ...
Page 65
Host Interface The microprocessor interface is used to relay configuration, control, status, and data information ® between the Intel LXT3108 LIU and an external microprocessor or micro controller. The microprocessor interface supports MPC860/M68360 (memory like bus), M68302 (standard Motorola ...
Page 66
Intel LXT3108 LIU 14.1.2 M68302 The M68302 (or the M68000 family) is supported in this mode. Notice that DTACK is not used in this case. The user is required to generate their own internal wait states when needed. The ...
Page 67
Interrupts There are four interrupt sources: 1. Status change in the Loss of Signal (LOS) bit of ® 08h. The Intel receiver signal and updates the specific LOS status bit to indicate presence or absence of a LOS condition. ...
Page 68
Intel LXT3108 LIU Figure 22. Interrupt Processing FlowChart LOS Read reg. 08h to get status of LOS No Is LOS active? Yes LOS Cleared LOS condition exists 68 Start No Enable Interrupts? Yes Write "1" into corresponding Write "0" ...
Page 69
Register Definitions ® Since the Intel LXT3108 LIU has both global registers and Page Port Registers (PPRs), the first subsection covers the global registers and the second subsection covers the PPRs. The global registers control parameters affecting operation for ...
Page 70
Intel LXT3108 LIU Table 18. Port Page Select Register, CPS, 00h Bit Name Bit 7 6..4 7-0 PS4-PS0 3..0 NOTE: When CPS Register value equals 9h. Reading of port page (PPR) registers is disabled. Table 19. ID Register, ID, ...
Page 71
Table 21. CLAD Configuration Register1, 11h Address Description CLAD_PSRST CLAD_PWDN CLAD_CSSEL CLAD_OT1E1 CLAD Configuration 3 11h Register 1 (CLAD_CONFIG1) CLAD_TFB CLAD_TRST NOTES: 1. Upon reset, restored default value is 00h the event that an accidental write of 1 ...
Page 72
Intel LXT3108 LIU Table 22. Port Page Register Bank Addresses Name Port Master Control Port Receiver Enable Transmit Control Receiver Control Termination Control RX Equalizer Status 0 RX Equalizer Status 1 RX Equalizer Status 2 LOS Window LOS Set ...
Page 73
Table 23. Port Master Control Page Register, 01h Address Description Name Port Master 01h MASTER Control NOTE: Upon reset, restored default value is 0h. G25 Table 24. Port Receiver Enable Page Register, 02h Address Description Name Port Receiver 02h RENEN ...
Page 74
Intel LXT3108 LIU Table 25. Transmit Control Page Register, 03h Address Description Name 03h Transmit Control TXCON NOTE: Upon reset, restored default value is 0h. Table 26. Receive Control Page Register, 04h Address Description Name RXSH MON_MOD 04h Receiver ...
Page 75
Table 27. Termination Control Page Register, 05h Address Description Name Termination 05h TERM Control TX/RX NOTE: Upon reset, restored default value is 0h. Table 28. Receiver Equalizer Status Zero Page Register, 06h Address Description Name RX Equalizer 06h RXSTATUS0 Status0 ...
Page 76
Intel LXT3108 LIU Table 31. LOS Window Page Register, 0Bh Address Description LOS Window for User Programmed LOS. Two modes of operation are available: 0Bh 1. User LOS with Amplitude Detection. Refer to Table 23. 2. User LOS with ...
Page 77
Table 34. Loopback Enable Page Register, 10h Address Description Name Loopback 10h LER Enable Register NOTE: Upon reset, restored default value is 0h. Table 35. Interrupt Enable Page Register, 11h Address Description Name Interrupt Enable 11h IER Register NOTE: Upon ...
Page 78
Intel LXT3108 LIU Table 37. Interrupt Status Two Page Register, 13h Address Description Name Interrupt Status 13h Register 2 NOTE: Upon reset, restored default value is 0h. Table 38. Line Coding Control One Page Register, 1Ch Address Description 1Ch ...
Page 79
Table 39. JA Control Two Page Register, 1Dh Address Description 1Dh Control Register 2 JA transmit or receive path JA enable NOTE: Upon reset, restored default value is 0h. Table 40. DJA Corner Frequency Selection JA Control Register T1/E1 Mode ...
Page 80
Intel LXT3108 LIU Table 43. Receiver Control Page Register, 3Ch Address Description Name 3Ch Receive Settings RWFCTRL NOTE: Upon reset, restored default value is 0h. Table 44. Transmit Coefficient Page Register Range, 40h-6Fh Address Description Name Transmit 40-6F Coefficients ...
Page 81
JTAG Boundary Scan ® The Intel LXT3108 LIU supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. 16.1 Architecture Figure 23 represents the Intel ® Figure 23. Intel ...
Page 82
Intel LXT3108 LIU Table 45. TAP State Description (Sheet State Update - DR Capture - IR Shift - IR Update - IR Pause - IR Pause - DR Exit1 - IR Exit1 - DR Exit2 - ...
Page 83
Figure 24. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE Datasheet 1 SELECT- CAPTURE- SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- ® Intel LXT3108 LIU 1 ...
Page 84
Intel LXT3108 LIU 16.3 JTAG Register Description The following paragraphs describe each of the registers represented in 16.3.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR ...
Page 85
Table 47. Instruction Register (IR) (Sheet Instruction SAMPLE/PRELOAD IDCODE BYPASS Datasheet Code # Comments Connects the BSR to TDI and TDO. The normal path between the ® 100 Intel LXT3108 LIU logic and the I/O pins is ...
Page 86
Intel LXT3108 LIU This page intentionally left blank. 86 Datasheet ...
Page 87
Test Specifications Table 48. Absolute Maximum Ratings Parameter 1 DC supply (reference to GND) Input voltage, RTIP/RRING Input voltage, any digital pin Input current, any pin Storage temperature Thermal Resistance, junction to ambient, QFP Thermal Resistance, junction to ambient, ...
Page 88
Intel LXT3108 LIU Table 50. Electrical Characteristics (Over Recommended Operating Conditions) Parameter 1 High level input voltage 1 Low level input voltage 2 Output High voltage 2 Output Low voltage Quiescent current Input leakage current Three-state leakage current (all ...
Page 89
Table 52. E1 Receiver Analog Characteristics Parameter Permissible cable attenuation Receiver (E1 SH/12 dB) sensitivity @ 1024 kHz (E1 LH/43 dB) (E1 line loss) Receiver dynamic range Signal to noise interference margin Loss of signal threshold Consecutive zeros before loss ...
Page 90
Intel LXT3108 LIU Table 53. T1 Transmitter Analog Characteristics (Sheet Parameter Transmit amplitude variation with power supply Difference between pulse sequences 1 Pulse width variation at half amplitude Line side short circuit current (T1) 10Hz - ...
Page 91
Table 54. T1 Receiver Analog Characteristics (Sheet Parameter Input termination resistor tolerance 39 KHz - 77KHz Input return 77- 1544 KHz 1 loss 1544 KHz - 2316 KHz 2 Receive intrinsic jitter, RCLK output Bipolar mode Receive ...
Page 92
Intel LXT3108 LIU Table 56. Jitter Attenuator Characteristics Parameter JACF=0 E1 jitter attenuator 3dB corner frequency JACF=1 JACF=0 T1 jitter attenuator 3dB corner frequency JACF=1 2 Jitter attenuator 3dB corner frequency Data latency delay Input jitter tolerance before FIFO ...
Page 93
Table 57. Receive Timing Characteristics for T1 Operation Parameter 2, 3 Receive clock duty cycle Receive clock pulse width T1 Receive clock pulse width High 1,3 T1 Receive clock pulse width Low RPOS/RNEG to RCLK rising time ...
Page 94
Intel LXT3108 LIU ® Figure 27. Intel LXT3108 LIU Output Jitter for CTR12/13 Applications 0.2 0.15 0.1 0. Figure 28. JTAG Timing TCK TMS TDI TDO Table 59. JTAG Timing Characteristics Parameter Cycle time ...
Page 95
Table 60. G.703 2.048 Mbps Pulse Mask Specifications Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse ...
Page 96
Intel LXT3108 LIU ® Figure 30. Intel LXT3108 LIU Jitter Tolerance Performance 1000 UI 100 4 1 TBD ...
Page 97
Figure 31. Intel LXT3108 LIU Jitter Transfer Performance 0 3Hz 0 dB -10 dB -20 dB -30 dB - ...
Page 98
Intel LXT3108 LIU 17.1 Microprocessor Interface Timing Diagrams Figure 32. MPC860 Write Timing Table 62. MPC860 Write Timing Characteristics Symbol Tadrs Tadrh Tadss Tadsh Trws Tcss Trwh Tds Tdh Trdys Trdyh 98 Parameter Address setup to clock Address hold ...
Page 99
Figure 33. MPC860 Read Timing Table 63. MPC860 Read Timing Characteristics Symbol Tadrsr Address setup to clock Tadrhr Address hold from clock Tadss TS# setup to clock Tadsh TS# hold from clock Trwsr R/W# setup to clock Tcss CS# setup ...
Page 100
Intel LXT3108 LIU Figure 34. M68302 Write Timing Table 64. M68302 Write Timing Characteristics Symbol Tadss Tadsh Trdss Trdsh Tddss Tddsh Tdsmin Tcsdss Tcsdsh 100 Parameter Address setup to LDS asserted Address hold from LDS asserted R/W# setup to ...
Page 101
Figure 35. M68302 Read Timing Table 65. M68302 Read Timing Characteristics Symbol Tadss Tadsh Trdss Trdsh Tdsdd Tdsdh Tdsmin Datasheet Parameter Address setup to LDS asserted Address hold from LDS assserted R/W# setup to LDS asserted R/W# hold from LDS ...
Page 102
Intel LXT3108 LIU ® TM Figure 36. Intel i486 /i960 CLK (MPI_CLK) ADR (AD) ADS# (DS) W/R# (RW) CS# (CS) Data (D(7:0)) RDY# (RDY) ® ® Figure 37. Intel i960 Muxed Mode Write Timing CLK (MPI_CLK) Tadrs AD (AD) ...
Page 103
TM Table 66. Intel i486 /i960 Symbol Tadrs Tadrh Tadss Tadsh Trws Trwh Tds Tdh Trdys Trdyh ® TM Figure 38. Intel i486 /i960 CLK (MPI_CLK) Tadrs ADR (AD) Tadsh Tadss ADS# (DS) W/R# (RW) CS# (CS) Data (D(7:0)) ...
Page 104
Intel LXT3108 LIU ® ® Figure 39. Intel i960 Muxed Mode Read Timing CLK (MPI_CLK) Tadrs AD (AD) Tadss ADS# (DS) W/R# (RW) CS# (CS) RDY# (RDY) ® TM Table 67. Intel i486 /i960 Symbol Tadrs Tadrh Tadss Tadsh ...
Page 105
Referenced Standards AT&T Pub 62411 Accunet T1.5 Service Bellcore TR-TSY-000009 Asynchronous Digital Multiplexes Requirements and Objectives Bellcore GR-253-CORE SONET Transport Systems Common Generic Criteria Bellcore GR-499-CORE Transport Systems Generic Requirements ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI ...
Page 106
Intel LXT3108 LIU This page intentionally left blank. 106 Datasheet ...
Page 107
Mechanical Specification ® Figure 40. Intel LXT3108 LIU 256 PBGA Mechanical Specification 17.00 ±0.10 7.00 REF PIN #A1 CORNER PIN #A1 ID 7.00 REF TOP VIEW SIDE VIEW Datasheet 1.00 REF 1. 0. ...
Page 108
Intel LXT3108 LIU ® Figure 41. Intel LXT3108 LIU 208 Pin QFP Mechanical Specifications 108 θ θ θ 3 ...
Page 109
Glossary Term Categories Term ADC AFE AGC ATWG BPV BSR BYR CLAD DAC DJA DSP FIR GUI HPS IADs IDR IMAPs IR JTAG LIU LH LH/SH LOS NRZ PBGA Datasheet Term definition Analog to Digital Converter Analog Front End ...
Page 110
Intel LXT3108 LIU POR PPR PPRB PPS PTM QFP SH TBD TAOS UI 110 Power On Reset Port Page Register Port Page Register Bank Port Page Select ® Intel Pulse Template Matching, Intel Quad Flat Pack Short Haul To ...