YMF744B-V Yamaha, YMF744B-V Datasheet

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YMF744B-V

Manufacturer Part Number
YMF744B-V
Description
3.3V; DS-1S: high performance audio controller for the PCI bus
Manufacturer
Yamaha
Datasheet

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YMF744B (DS-1S) is a high performance audio controller for the PCI Bus. DS-1S consists of two separated
functional blocks. One is the PCI Audio block and the other is the Legacy Audio block. PCI Audio block
allows Software Driver to handle maximum of 73 concurrent audio streams with the Bus Master DMA engine.
The PCI Audio Engine converts the sampling rate of each audio stream and the streams are mixed without
utilizing the CPU or causing system latency. By using the Software Driver from YAMAHA, PCI Audio
provides 64-voice XG wavetable synthesizer with Reverb and variation. It also supports DirectSound hardware
accelerator, Downloadable Sound (DLS) and DirectMusic accelerator.
Legacy Audio block supports FM Synthesizer, Sound Blaster Pro, MPU401 UART mode and Joystick
function in order to provide hardware compatibility for numerous PC games on real DOS without any software
driver. To achieve legacy DMAC compatibility on the PCI, DS-1S supports both PC/PCI and Distributed
DMA protocols. DS-1S also supports Serialized IRQ for legacy IRQ compatibility.
DS-1S supports the connection to AC’97 which provides high quality DAC, ADC and analog mixing, and it
can connect two AC’97s. In addition, it supports consumer IEC958, Audio Digital Interface (SPDIF), to
connect external audio equipment by digital.
• PCI 2.2 Compliant
• PC’98/PC’99 specification Compliant
• PCI Bus Power Management rev. 1.0 Compliant
• Supports clock run
• PCI Bus Master for PCI Audio
• Legacy Audio compatibility
• Supports Serialized IRQ
(Support D0, D2 and D3 state)
OVERVIEW
FEATURES
True Full Duplex Playback and Capture with
different Sampling Rate
Maximum 64-voice XG capital Wavetable
Synthesizer including GM compatibility
DirectSound Hardware Acceleration
DirectMusic Hardware Acceleration
Downloadable Sound (DLS) level-1
FM Synthesizer
Hardware Sound Blaster Pro compatibility
MPU401 UART mode MIDI interface
Joystick
without prior notice. When using this device, please recheck the specifications.
The contents of this catalog are target specifications and are subject to change
YMF744B
YAMAHA CORPORATION
DS-1S
• Supports PC/PCI and Distributed DMA for legacy
• Supports I
• Supports Consumer IEC958 Output (SPDIF OUT)
• Supports Consumer IEC958 Input (SPDIF IN)
• Supports AC’97 Interface (AC-Link) Revision 2.1
• AC’97 Digital Docking
• Supports 4-Channel Speaker
• Hardware Volume Control
• EEPROM Interface
• Single Crystal operation (24.576MHz)
• 3.3V Power supply (5V tolerant)
• 128-pin LQFP
DMAC (8237) emulation
2
S serial input for Zoomed Video Port
YMF744B-V : 0.5mm pin pitch
YMF744B-R : 0.4mm pin pitch
CATALOG No.:LSI-4MF744B00
YMF744B CATALOG
February 3, 1999
December 18, 1998
Preliminary

YMF744B-V Summary of contents

Page 1

... AC’97 Digital Docking • Supports 4-Channel Speaker • Hardware Volume Control • EEPROM Interface • Single Crystal operation (24.576MHz) • 3.3V Power supply (5V tolerant) • 128-pin LQFP YMF744B-V : 0.5mm pin pitch YMF744B-R : 0.4mm pin pitch CATALOG No.:LSI-4MF744B00 Preliminary YMF744B CATALOG December 18, 1998 February 3, 1999 ...

Page 2

... YMF744B LOGOS GENERAL MIDI logo is a trademark of Association of Musical Electronics Industry (AMEI), and indicates GM system level 1 Compliant. XG logo is a trademark of YAMAHA Corporation. SONDIUS-XG logo is a trademark that Stanford University in the United States and YAMAHA Corporation hold jointly. Sensaura logo is a trademark of Central Research Laboratories Limited. ...

Page 3

... YMF744B PIN CONFIGURATION YMF744B-V (0.5mm pin pitch) AD26 1 PVDD2 2 AD25 3 AD24 4 CBE3# 5 IDSEL 6 AD23 7 PVSS4 8 AD22 9 AD21 10 AD20 11 AD19 12 AD18 13 AD17 14 AD16 15 CBE2# 16 PVSS3 17 FRAME# 18 IRDY# 19 TRDY# 20 DEVSEL# 21 PVDD1 22 STOP# 23 PERR# 24 SERR# 25 PAR 26 CBE1# 27 PVSS2 28 AD15 29 AD14 30 AD13 31 AD12 32 AD11 33 AD10 ...

Page 4

... YMF744B YMF744B-R (0.4mm pin pitch) AD24 1 CBE3# 2 IDSEL 3 AD23 4 PVSS4 5 AD22 6 AD21 7 AD20 8 AD19 9 AD18 10 AD17 11 AD16 12 CBE2# 13 PVSS3 14 FRAME# 15 IRDY# 16 TRDY# 17 DEVSEL# 18 PVDD1 19 STOP# 20 PERR# 21 SERR# 22 PAR 23 CBE1# 24 PVSS2 25 AD15 26 AD14 27 AD13 28 AD12 29 AD11 30 AD10 31 AD9 32 128 Pin LQFP Top View ...

Page 5

... YMF744B PIN DESCRIPTION 1. PCI Bus Interface (54-pin) Name I/O PCICLK I RST# I AD[31:0] IO C/BE[3:0]# IO PAR IO FRAME# IO IRDY# IO TRDY# IO STOP# IO IDSEL I DEVSEL# IO REQ# O GNT# I PCREQ# O PCGNT# I PERR# IO SERR# O INTA# O SERIRQ# IO CLKRUN AC’97 Interface (8-pin) Name I/O CRST# O CMCLK O CBCLK I CSDO O CSYNC O CSDI0 I CSDI2 I DOCKEN# I Type ...

Page 6

... YMF744B 3. External Audio Interface (5-pin) Name I/O SPDIFOUT O SPDIFIN I ZVBCLK I ZVLRCK I ZVSDI I 4. Legacy Device Interface (15-pin) Name I/O IRQ5 O IRQ7 O IRQ9 O IRQ10 O IRQ11 O GP[3:0] I GP[7:4] I RXD I TXD O 5. Miscellaneous (11-pin) Name I/O ROMCS O ROMSK / VOLUP# IO ROMDO / VOLDW# IO ROMDI I XI24 I XO24 O LOOPF I GPIO[2:0] IO TEST# I Type ...

Page 7

... YMF744B 6. Power Supply (22-pin) Name I/O PVDD[3:0] - PVSS[6:0] - CVDD[2:0] - VDD[2:0] - VSS[3:0] - LVDD - 7. Reserve Pin (13-pin) Name I/O RESERVE0 O RESERVE[3:2] I RESERVE[16:8,1] - TYPE T : TTL Ttr : Tri-State TTL Tup : Pull up (Max. 300kohm) TTL Type Size - - 3.3V Power supply for PCI Bus Interface - - Ground for PCI Bus Interface ...

Page 8

... YMF744B BLOCK DIAGRAM EEPROM I/F GPIO PCI Side Band Legacy Audio PC/PCI S-IRQ PCI Interface Audio Function Config Register PCI Native Audio SPDIF Input ZV Port FM Synthesizer SB Pro D-DMA Engine MPU401 Joystick PCI Bus Master DMA Controller XG Synthesizer DirectSound Acc. Wave In/Out -8- SPDIF ...

Page 9

... YMF744B FUNCTION OVERVIEW 1. PCI INTERFACE DS-1S supports the PCI bus interface and complies to PCI revision 2.2. 1-1. PCI Bus Command DS-1S supports the following PCI Bus commands. 1-1-1. Target Device Mode C/BE[3:0 ...

Page 10

... YMF744B 1-2. PCI Configuration Register In addition to the Configuration Register defined by PCI Revision 2.2, DS-1S provides proprietary PCI Configuration Registers in order to control legacy audio function, such as FM Synthesizer, Sound Blaster Pro, MPU401 and Joystick. These additional registers are configured by BIOS or the configuration software from YAMAHA Corporation. ...

Page 11

... YMF744B 00-01h: Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Vendor ID This register contains the YAMAHA Vendor ID registered in Revision 2.2. This register is hardwired to 1073h. 02-03h: Device ID Read Only Default: 0010h Access Bus Width: 8, 16, 32-bit b15 ...

Page 12

... YMF744B b6................PER: Parity Error Response This bit enables DS-1S responses to Parity Error. “0”: DS-1S ignores all parity errors. “1”: DS-1S performs error operation when DS-1S detects a parity error. b8................SER: SERR# Enable This bit enables DS-1S to drive SERR#. “0”: Do not drive SERR#. “1”: Drives SERR# when DS-1S detects an Address Parity Error on normal target cycle or a Data Parity Error on special cycle ...

Page 13

... YMF744B 08h: Revision ID Read Only Default: 02h Access Bus Width: 8, 16, 32-bit Revision ID b[7:0] ..........Revision ID This register contains the revision number of DS-1S. This register is hardwired to 02h. 09h: Programming Interface Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Programming Interface b[7:0] ...

Page 14

... YMF744B 0Dh: Latency Timer Read / Write Default: 00h Access Bus Width: 8, 16, 32-bit Latency Timer b[7:0] ..........Latency Timer When DS-1S becomes a Bus Master device, this register indicates the initial value of the Master Latency Timer. 0Eh: Header Type Read Only Default: 00h ...

Page 15

... YMF744B 14-17h: Legacy Audio I/O Base Address (Dummy for SB, FM, MPU, D-DMA) Read / Write Default: 00000001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b31 b30 b29 b28 - - - - b0................IO (Read Only) This bit indicates that the base address is assigned to I/O. This bit is hardwired to “1”. ...

Page 16

... YMF744B 2C-2Dh: Subsystem Vendor ID Read Only Default: 1073h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:0] ........Subsystem Vendor ID This register contains the Subsystem Vendor ID. In general, this ID is used to distinguish adapters or systems made by different IHVs using the same chip by the same vendor. This register is read only. To write the IHV’ ...

Page 17

... YMF744B 34h: Capability Register Pointer Read Only Default: 50h Access Bus Width: 8, 16, 32-bit Capability Register Pointer b[7:0] ..........Capability Register Pointer This register indicates the offset address of the Capabilities register in the PCI Configuration register when 58-59h: ACPI Mode register, ACPI bit is “0”. DS-1S provides PCI Bus Power Management registers as the capabilities. The Power Management registers are mapped to 50h - 57h in the PCI Configuration register, and this register indicates “ ...

Page 18

... YMF744B 3Fh: Maximum Latency Read Only Default: 19h Access Bus Width: 8, 16, 32-bit Maximum Latency b[7:0] ..........Maximum Latency This register indicates how often DS-1S generates the Bus Master Request. This register is hardwired to 19h. 40-41h: Legacy Audio Control Read / Write Default: 907Fh ...

Page 19

... YMF744B b4................MIEN: MPU401 IRQ Enable This bit enables the interrupt service of MPU401, when LAD is set to “0” and MEN is set to “1”. MPU401 generates an interrupt signal when it receives any kind of MIDI data from the RXD pin. “0”: The MPU401 block can not use the interrupt service. ...

Page 20

... YMF744B b14..............SIEN: Serialized IRQ enable DS-1S supports 3 types of interrupt protocols: PCI interrupt (INTA#), Legacy interrupt (IRQs) and Serialized IRQ. The interrupt protocol is selected with IMOD and SIEN as follows. The interrupt channels for IRQs and Serialized IRQ are determined by SBIRQ and MPUIRQ,. Only one protocol can be used at once ...

Page 21

... YMF744B b[14:13] ......SBVER: SB Version Select These bits set the version of the SB Pro DSP. The value set in these bits is returned by sending the E1h DSP command. “0”: ver 3.01 “1”: ver 2.01 “2”: ver 1.05 “3”: reserved b15..............IMOD: Legacy IRQ mode The legacy interrupt protocol is selected with IMOD and SIEN. Refer to the explanation of SIEN bit. ...

Page 22

... YMF744B 48-49h: DS-1S Control Read / Write Default: 0001h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - - b0................CRST: AC’97 Software Reset Signal Control This bit controls the CRST# signal. “0”: Inactive (CRST#=High) “1”: Active (CRST#=Low) b2................WRST: AC’97 Warm Reset This bit places the AC’ ...

Page 23

... YMF744B 4A-4Bh: DS-1S Power Control 1 Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 PR7 PR6 PR5 PR4 b0................DMC: Disable Master Clock Oscillation Setting this bit to “1” disables the oscillation of the Master Clock (24.576 MHz). “0”: Normal (default) “ ...

Page 24

... YMF744B b12..............PR4: AC’97 Power Down Control 4 This bit controls the power state of the AC-link in the Primary AC’97. “0”: Normal (default) “1”: Power down b13..............PR5: AC’97 Power Down Control 5 Setting this bit to “1” disables the internal clock of the Primary AC’97. In case the AC’97 is used with DS-1S, the master clock is supplied from DS-1S. Therefore, when the clock is stopped completely, set PR5 bits to “ ...

Page 25

... YMF744B 4E-4Fh: DS-1S Power Control 2 Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - PSHWV b0................CMCD: CODEC Master Clock Disable Setting this bit to “1” disables the oscillation of the CMCLK. To stop a clock, when the CMCLK is supplied to the AC’97 required that b13:PR5 bit of 4A-4Bh register is set to “1”. (If the Secondary AC’ ...

Page 26

... YMF744B b7................PSZV: Power Save Zoomed Video port Setting this bit to “1” stops a clock supplied to the Zoomed Video port block. “0”: Normal (default) “1”: Disable b8................PSDIT: Power Save Digital Audio Interface Transmitter Setting this bit to “1” stops a clock supplied to the DIT block. ...

Page 27

... YMF744B Master Clock (24.576MHz) DMC PCI Clock (33MHz) External Input 50h: Capability ID Read Only Default: 01h Access Bus Width: 8, 16, 32-bit Capability ID b[7:0] ..........Capability ID: Capability Identifier This register indicates that the new capability register is for Power Management control. This register is hardwired to 01h ...

Page 28

... YMF744B 51h: Next Item Pointer Read Only Default: 00h Access Bus Width: 8, 16, 32-bit Next Item Pointer b[7:0] ..........Next Item Pointer DS-1S does not provide other new capability besides Power Management. This register is hardwired to 00h. 52-53h: Power Management Capabilities Read Only ...

Page 29

... YMF744B 58-59h: ACPI Mode Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 - - - - b0................ACPI: ACPI Mode Select This bit select either PCI Bus Power Management or ACPI Mode for power management of DS-1S. “0”: PCI Bus Power Management is used. CAP bit (06-07h: Status Register) and Capabilities Pointer (34h) are enabled. “ ...

Page 30

... YMF744B b4................SPR4: Secondary AC’97 Power Down Control 4 This bit controls the power state of the AC-link in the Secondary AC’97. “0”: Normal (default) “1”: Power down b5................SPR5: Secondary AC’97 Power Down Control 5 Setting this bit to “1” disables the internal clock of the Secondary AC’97. In case the AC’97 is used with DS-1S, the master clock is supplied from DS-1S. Therefore, when the clock is stopped completely, set SPR5 bits to “ ...

Page 31

... YMF744B 64-65h: MPU401 Base Address Read / Write Default: 0000h Access Bus Width: 8, 16, 32-bit b15 b14 b13 b12 b[15:1] ........MPU401 Base Address This register sets the base address of the MPU401. If b5:I/O bit of 40h register is set to “1”, b[9:1] bits are decoded by ignoring b[15:10] bits. 66-67h: Joystick Base Address ...

Page 32

... YMF744B 2. ISA Compatible Device DS-1S contains the following functions to maintain the compatibility with the past ISA Sound Devices. These devices are considered Legacy devices and the functions are referred to as Legacy Audio. Legacy Audio is independent from PCI Audio and can be used simultaneously. ...

Page 33

... YMF744B DS-1S supports PC/PCI and D-DMA protocols to emulate the DMA of SB Pro on the PCI. In addition, DS- 1S supports the old type of interrupts used by ISA and the Serialized IRQ protocol. Yamaha recommends the combination of PC/PCI and Serialized IRQ. The system block diagram when using Intel chip set is shown below. ...

Page 34

... YMF744B 2-1. FM Synthesizer Block FM Synthesizer Block is register compatible with YMF289B. However, Power Management register has been deleted because it is now controlled by the PCI Configuration Register. The following shows the FMBase I/O map of FM Synthesizer. FMBase (R) FMBase (W) FMBase+1 (R/W) FMBase+2 (W) FMBase+3 (R/W) The default FMBase value is 0x0388. ...

Page 35

... YMF744B 2-1-2. FM Synthesizer Data Register FM Synthesizer Data Register Array 0 (R/W): Address D7 D6 00-01h 02h 03h 04h RST MT1 08h - NTS (*1) 20-35h AM VIB (*2) 40-55h KSL (*3) 60-75h (*4) 80-95h A0-A8h B0-B8h - - BDh DAM DVB C0-C8h *6 *6 (*5) E0-F5h - - FM Synthesizer Data Register Array 1 (R/W) Address D7 D6 00-01h 04h - - 05h ...

Page 36

... YMF744B 2-2. Sound Blaster Pro Block This block emulates the DSP commands of Sound Blaster and Sound Blaster Pro. Only playback functions are supported (record functions are not supported). However, to maintain compatibility for games designed so that every DSP command receives a correct response. ...

Page 37

... YMF744B 2-2-1. DSP Command The following shows the list of DSP Commands that are supported by the SB Pro engine. Both SB and SB Pro commands are supported. CMD Support Function 10h o 8bit direct mode single byte digitized sound output 14h o 8bit single-cycle DMA mode digitized sound output ...

Page 38

... YMF744B 2-2-2. Sound Blaster Pro Mixer The following shows the register map of the Mixer section of Sound Blaster Pro. Address b7 b6 00h 04h Voice Volume L 0Ah - - 0Ch - - 0Eh - - 22h Master Volume L 26h MIDI Volume L 28h CD Volume L* 2Eh Line Volume L* F0h SBPDA - F1h F8h ...

Page 39

... YMF744B (1) Volume for MIDI 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute 6 0000h mute 7 0000h The default is Master = 4, MIDI = 4 (-12dB). (2) Volume for Voice 0 mute 0 0000h mute 1 0000h mute 2 0000h mute 3 0000h mute 4 0000h mute 5 0000h mute ...

Page 40

... YMF744B 2-2-3. SB Suspend / Resume The SB block can read the internal state as to support Suspend and Resume functions. The internal state is made up of 268 flip flops. To read the state, these states are shifted in order and read 8 bits at a time from the SCAN DATA register. ...

Page 41

... YMF744B F1h: Scan In/ Out Data Read / Write Default: 00h SCAN DATA b[7:0] ..........SCAN DATA This is the data port for reading and writing the internal state. F2h: Current FM Synthesizer Index Read Only Default: 00h Current FM Synthesizer Index b[7:0] ..........Current FM Synthesizer Index This register indicates current index of the FM Synthesizer ...

Page 42

... YMF744B b7................FFEMP: FM Synthesizer Empty This bit indicates whether or not FIFO followed by the FM Synthesizer is empty. “0”: not Empty “1”: Empty (default) i) Scan Out SBPDA=0 SBPDR=1 SBPDA=1 SM=1 SS=1 SE=1 -> 0 Scan Data (Read) Suspend Preparation byte (Total Scan Data = 268 bit (33 byte bit)) ...

Page 43

... YMF744B 2-2-4. SB IRQ Status F8h: Interrupt Flag Register Read Only Default: 00h b0................SBI: SB Interrupt Flag This bit indicates that the SB DSP occurs the interrupt. This bit is read only. Thus, read the SB DSP read port to clearing the interrupt and this bit. Then, the value of the read port is invalid. ...

Page 44

... YMF744B 3. DMA Emulation Protocol The former synthesizer LSI for the ISA bus such as the Sound Blaster used the DMA controller (8237: ISA DMAC) on the system to transfer the sound data from/to the host. For DS-1S, however, ISA DMAC must be used to transfer the sound data to the Sound Blaster Pro Block of the Legacy Audio Block ...

Page 45

... YMF744B 3-2. D-DMA DS-1S provides the following registers to support D-DMA. D-DMA Slave Configuration Register (4C- 4Dh) of the PCI Configuration register is used to set the Base address of the Slave Address. Slave Address Base + 0h Base + 0h Base + 1h Base + 1h Base + 2h Base + 2h Base + 3h Base + 3h Base + 4h Base + 4h Base + 5h Base + 5h Base + 6h Base + 6h ...

Page 46

... YMF744B 4. Interrupt Routing DS-1S supports three types of interrupts, interrupt signal on the PCI bus (INTA#), interrupt signal on the ISA bus (IRQ[5,7,9,10,11]), and Serialized IRQ. The IRQs on DS-1S are routed as shown below. INTA# INTA IRQ5 IRQ7 ISA IRQ IRQ9 IRQ10 IRQ11 SERIRQ# SERIRQ PCI Audio can only use INTA#, but the Sound Blaster Pro and MPU401 blocks of the Legacy Audio Block can use any of the three protocols ...

Page 47

... YMF744B 5. Hardware Volume Control The hardware volume control determines the AC’97 master volume without using any software control using the external circuit listed below. Two pins, VOLUP# for increasing the volume and VOLDW# for decreasing the volume, are used. DS-1S provides a shadow register for the AC’97 master volume. When the software accesses the AC’97 master volume always reflected in the shadow register ...

Page 48

... YMF744B 6. Digital Audio Interface DS-1S supports each system of the SPDIF input/output port compliant with the IEC958 specification. 6-1. SPDIF IN DS-1S provides the SPDIF input capability by switch-over operation of the zoomed video port. SPDIF input sampling frequency is 32.0kHz, 44.1kHz or 48.0kHz. In DS-1S, sampling rate of the SPDIF signal incoming from the SPDIFIN pin is converted to 48.0kHz in the frequency rate conversion stage in order to process all the signals at 48 ...

Page 49

... YMF744B 7. Zoomed Video Port Zoomed Video Port is defined in the PC Card Standard (PCMCIA) applicable to the notebook PC or other systems. This port is used to directly output video and/or audio signals onto the PCMCIA bus for D/A conversion process, and connect them directly to the video and/or audio signal processing chips on the PC system ...

Page 50

... YMF744B 8. Multiple AC’97 & Multi-Channel DS-1S allows connection with up to two AC’97s, and plays back up to 4-channel PCM data. Therefore, the following applications can be realized. 8-1. AC’97 Digital Docking AC’97 digital docking can be realized by mounting the secondary AC’97 on the docking station side. Typical example of digital docking connection between DS-1S and AC’97s is represented in the circuit diagram below ...

Page 51

... YMF744B ELECTRICAL CHARACTERISTICS 1. Absolute Maximum Ratings Item Power Supply Voltage (PVDD, VDD, CVDD, LVDD) Input Voltage Operating Ambient Temperature Storage Temperature Note : PVSS=VSS=0[V] 2. Recommended Operating Conditions Item Power Supply Voltage (PVDD, VDD, CVDD, LVDD) Operating Ambient Temperature Note : PVSS=VSS=0[V] Symbol Min. ...

Page 52

... YMF744B 3. DC Characteristics Item High Level Input Voltage 1 High Level Input Voltage 1 Low Level Input Voltage 1 High Level Input Voltage 2 Low Level Input Voltage 2 High Level Input Voltage 3 Low Level Input Voltage 3 High Level Input Voltage 4 Low Level Input Voltage 4 Input Leakage Current ...

Page 53

... YMF744B 4. AC Characteristics 4-1. Master Clock (Fig.1) Item XI24 Cycle Time XI24 High Time XI24 Low Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0.3 V XI24 4-2. Reset (Fig.2) Item Reset Active Time after Power Stable Power Stable to Reset Rising Edge Reset Slew Rate Note : Top = 0-70° ...

Page 54

... YMF744B 4-3. PCI Interface (Fig.3, 4) Item PCICLK Cycle Time PCICLK High Time PCICLK Low Time PCICLK Slew Rate PCICLK to Signal Valid Delay Float to Active Delay Active to Float Delay Input Setup Time to PCICLK Input Hold Time for PCICLK Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0 *11: This characteristic is applicable to REQ# and PCREQ# signal ...

Page 55

... YMF744B 4-4. AC’97 Master Clock Item CMCLK Cycle Time CMCLK High Time CMCLK Low Time CMCLK Rising Time CMCLK Falling Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0 CMCLK (Fig.5) Symbol Min. Typ 40.69 CMCYC CMHIGH t 8 CMLOW ...

Page 56

... YMF744B 4-5. AC-link (Fig.6) Item CBCLK Cycle Time CBCLK High Time CBCLK Low Time CSYNC Cycle Time CSYNC High Time CSYNC Low Time CBCLK to Signal Valid Delay Output Hold Time for CBCLK Input Setup Time to CBCLK Input Hold Time for CBCLK Warm Reset Width Note) Top = 0-70° ...

Page 57

... YMF744B 4-6. Zoomed Video Port Item ZVLRCK Delay Time ZVLRCK Setup Time ZVBCLK Low Time ZVBCLK High Time ZVSDI Setup Time ZVSDI Hold Time Note : Top = 0-70°C, PVDD=3.3±0.3 V, VDD=3.3±0.3 V, CVDD=3.3±0.3 V, LVDD=3.3±0 ZVLRCK ZVSCLK ZVSDI (Fig.7) Symbol Min. ...

Page 58

... YMF744B EXTERNAL DIMENSIONS YMF744B-V 102 103 128 1 P-0.50Typ. The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. ...

Page 59

... YMF744B YMF744B-R LEAD THICKNESS : 0.125Typ. or 0.15Typ. The shape of the molded corner may slightly different from the shape in this diagram. The figure in the parenthesis ( ) should be used as a reference. Plastic body dimensions do not include burr of resin. UNIT : mm Note : The LSIs for surface mount need especial consideration on storage and soldering conditions. ...

Page 60

... YMF744B 1. Yamaha reserves the right to make changes to its Products and to this document without notice. The information contained in this document has been carefully checked and is believed to be reliable. However, Yamaha assumes no responsibilities for inaccuracies and makes no commitment to update or to keep current the information contained in this document ...

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