S29AL016M90FAI010 SPANSION, S29AL016M90FAI010 Datasheet
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S29AL016M90FAI010
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S29AL016M90FAI010 Summary of contents
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S29AL016M 16 Megabit ( 8-Bit 16-Bit) 3.0 Volt-only Boot Sector Flash Memory featuring MirrorBit technology TM Data Sheet Distinctive Characteristics Architectural Advantages Single power supply operation — for read, erase, and program operations Manufactured ...
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General Description The S29AL016M Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in a 48-ball Fine-pitch BGA, 64- ball Fortified BGA, and 48-pin TSOP packages. The word-wide data (x16) ...
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Table of Contents S29AL016M 2 General Description 3 Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . ...
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Product Selector Guide Family Part Number Speed Option Full Voltage Range: V Max access time (ns) Max CE# access time (ns) Max OE# access time (ns) Notes: 1. See “AC Characteristics” for full specifications. 2. Contact sales office or representative ...
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Connection Diagrams A15 1 A14 2 A13 3 A12 4 A11 5 A10 A19 WE# 11 RESET RY/BY# 15 A18 16 A17 ...
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Connection Diagrams A6 B6 A13 A12 WE# RESET RY/BY A17 Fine-pitch BGA Top View, Balls Facing Down A14 A15 ...
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Connection Diagrams A12 A13 RESET# WE# A4 RY/BY A17 Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP, BGA, SSOP, PDIP, ...
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Pin Configuration A19–A0 DQ14–DQ0 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY Logic Symbol addresses = 15 data inputs/outputs = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) = Selects ...
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... Ordering Information Standard Products Spansion standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. S29AL016M DEVICE NUMBER/DESCRIPTION S29AL016M 16 Megabit (2M x 8-Bit/1M x 16-Bit) MirrorBit 3.0 Volt-only Read, Program, and Erase ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is com- posed of ...
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The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the mem- ory content occurs during the power transition. No command is necessary in this ...
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The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V ± 0.3 V. (Note that this is a more restricted voltage range than CE# and RESET# are held ...
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Table 2. Sector Address Tables (Model 01, Top Boot Device) Sector A19 A18 A17 A16 A15 A14 A13 A12 SA0 SA1 SA2 SA3 SA4 ...
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Table 3. Sector Address Tables (Model 02, Bottom Boot Device) Sector A19 A18 A17 A16 A15 A14 A13 A12 SA0 SA1 SA2 SA3 SA4 ...
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... To access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in Tables 10–11. This method does not require V lect mode. Table 4. Autoselect Codes (High Voltage Method) Description Mode CE# OE# WE# Manufacturer ID L (Spansion Products) Device ID: Word L S29AL016M (Model 01) Byte L (Top Boot Block) Device ID: ...
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Sector protection and unprotection requires V be implemented either in-system or via programming equipment. the algorithms and dard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. ...
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START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address with ...
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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 256 bytes in length, and uses a ...
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RESET# may be at either V tion of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. To verify the protect/unprotect status of the ...
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Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address 55h in word mode (or ...
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Addresses Addresses (Word Mode) (Byte Mode) 1Bh 36h 1Ch 38h 1Dh 3Ah 1Eh 3Ch 1Fh 3Eh 20h 40h 21h 42h 22h 44h 23h 46h 24h 48h 25h 4Ah 26h 4Ch Note: CFI data related to timeouts may differ from actual ...
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Table 9. Primary Vendor-Specific Extended Query Addresses Addresses (Word Mode) (Byte Mode) 40h 80h 41h 82h 42h 84h 43h 86h 44h 88h 45h 8Ah 46h 8Ch 47h 8Eh 48h 90h 49h 92h 4Ah 94h 4Bh 96h 4Ch 98h Hardware Data ...
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Logical Inhibit Write cycles are inhibited by holding any one of OE initiate a write cycle, CE# and WE# must be a logical zero while OE logical one. Power-Up Write Inhibit If ...
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... Programming is allowed in any sequence and across sector boundaries. Program- ming to the same address multiple times without intervening erases is limited. For such application requirements, please contact your local Spansion represen- tative. Any bit in a word or byte cannot be programmed from “0” back to a “ ...
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Only erase operations can convert a “0” “1”. Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster ...
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Notes: See Tables 10 and 11 for program command sequence. Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. ...
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Figure 5 illustrates the algorithm for the erase operation. See the Operations tables in ing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, ...
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Suspend command is ignored if written during the chip erase operation or Em- bedded Program algorithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Addresses are “don’t-cares” when ...
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Notes: 1. See Tables 10–11 2. See “DQ3: Sector Erase Timer” Program Suspend/Program Resume Command Sequence The Program Suspend command allows the system to interrupt a programming operation so that data can be read from any non-suspended sector. When the ...
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DQ7 or DQ6 status bits, just as in the standard program operation. See Operation Status The system must write the Program Resume command (address bits are don’t care) to exit the Program Suspend mode and continue the programming opera- tion. ...
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Command Definitions Tables Table 10. Command Definitions (x16 Mode, BYTE Command Sequence (Note 1) Read (Note 5) 1 Reset (Note 6) 1 Manufacturer ID 4 Device ID, Top Boot (Note 8) 6 Device ID, Bottom Boot (Note 8) ...
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Table 11. Command Definitions (x8 Mode, BYTE Command Sequence (Note 1) Read (Note 5) 1 Reset (Note 6) 1 Manufacturer ID 4 Device ID, Top Boot (Note 8) 6 Device ID, Bottom Boot (Note 6 8) SecSi™ Sector ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table describe the functions of these bits. DQ7, RY/BY#, and DQ6 each offer a method for determining ...
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No Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should ...
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If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend ...
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Figure 8 shows the toggle bit algorithm in flowchart form, and the section ing Toggle Bits DQ6/DQ2” subsection. Figure 20 differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 8 gins reading toggle bit ...
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Notes: 1. Read toggle bit twice to determine whether or not it is toggling. See text. 2. Recheck toggle bit because it may stop toggling as DQ5 changes to “1”. See text. DQ5: Exceeded Timing Limits DQ5 indicates whether the ...
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Under this condition, the device halts the opera- tion, and when the operation has exceeded the timing limits, DQ5 produces a “1.” Under both these conditions, the system must issue the reset command ...
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Absolute Maximum Ratings Storage Temperature, Plastic Packages . . . . . . . . . . . . . . . . .–65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . ...
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DC Characteristics CMOS Compatible Parameter Description I Input Load Current Input Load Current LIT Reset Leakage Current Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write ...
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Test Conditions Device Under Test C L 6.2 kΩ Note: Diodes are IN3064 or equivalent Figure 11. Test Setup Key to Switching Waveforms WAVEFORM Don’t Care, Any Change Permitted V CC 0.5 V Input CC 0.0 V Figure 12. Input ...
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AC Characteristics Read Operations Parameter JEDEC Std Description t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output ...
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AC Characteristics Hardware Reset (RESET#) Parameter JEDEC Std Description RESET# Pin Low (During Embedded Algorithms READY Read or Write (See Note) RESET# Pin Low (NOT During Embedded Algorithms) t READY to Read or Write (See Note) t RESET# ...
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AC Characteristics Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH ...
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AC Characteristics Program Command Sequence (last two cycles Addresses 555h CE# OE# WE Data RY/BY VCS Notes program address program data Illustration shows device in word ...
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AC Characteristics Erase Command Sequence (last two cycles Addresses 2AAh CE# OE# WE Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data ...
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AC Characteristics t RC Addresses ACC POLL OE# t OEH WE# DQ7 DQ0–DQ6 t BUSY RY/BY# Note Valid address. Illustration shows first status cycle after command sequence, last ...
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AC Characteristics Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Temporary Sector ...
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AC Characteristics RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# Note: For sector protect For sector unprotect ...
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AC Characteristics Alternate CE# Controlled Erase/Program Operations Parameter JEDEC Std Description t t Write Cycle Time (Note 1) AVAV Address Setup Time AVEL Address Hold Time ELAX Data Setup Time DVEH ...
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AC Characteristics 555 for program 2AA for erase Addresses WE# OE# CE Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written ...
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Erase and Programming Performance Parameter Sector Erase Time Chip Erase Time Byte Programming Time Word Programming Time Byte Mode Chip Programming Time (Note 3) Word Mode Notes: 1. Typical program and erase times assume the following conditions: 25 pattern. 2. ...
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Physical Dimensions TS 048—48-Pin Standard TSOP Note: BSC is an ANSI standard for Basic Space Centering. April 21, 2004 S29AL016M_00A4 Dwg rev AA; 10/99 S29AL016M 54 ...
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Physical Dimensions TSR048—48-Pin Reverse TSOP Note: BSC is an ANSI standard for Basic Space Centering. 55 S29AL016M Dwg rev AA; 10/99 S29AL016M_00A4 April 21, 2004 ...
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Physical Dimensions FBA048—48-Ball Fine-Pitch Ball Grid Array (BGA Package Note: BSC is an ANSI standard for Basic Space Centering. April 21, 2004 S29AL016M_00A4 S29AL016M Dwg rev AF; 10/99 56 ...
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Physical Dimensions LAA064—64-Ball Fortified Ball Grid Array (BGA Package Note: BSC is an ANSI standard for Basic Space Centering. 57 S29AL016M S29AL016M_00A4 April 21, 2004 ...
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Revision Summary Revision A (January 30, 2004) Initial release. Revision (February 20, 2004) Product Selector Guide Removed regulated voltage range for the Speed Option. Ordering Information Included explanations of the package markings for TSOP and BGA packages. ...
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... Trademarks and Notice The contents of this document are subject to change without notice.This document may contain information on a Spansion product under development by FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory ...
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April 21, 2004 S29AL016M_00A4 S29AL016M 60 ...