IS42S32800B Integrated Silicon Solution, IS42S32800B Datasheet

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IS42S32800B

Manufacturer Part Number
IS42S32800B
Description
IS42S32800B2M Words x 32 Bits x 4 Banks (256-MBIT) SYNCHRONOUS DYNAMIC RAM
Manufacturer
Integrated Silicon Solution
Datasheet

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IS43R16800A
FEATURES
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. 00A
07/11/05
8Meg x 16
128-MBIT DDR SDRAM
Clock Frequency: 200, 125 MHz
Power supply (V
SSTL 2 interface
Four internal banks to hide row Pre-charge
and Active operations
Commands and addresses register on positive
clock edges (CLK)
Bi-directional Data Strobe signal for data cap-
ture
Differential clock inputs (CLK and CLK) for
two data accesses per clock cycle
Data Mask feature for Writes supported
DLL aligns data I/O and Data Strobe transitions
with clock inputs
Half-strength and Matched drive strength
options
Programmable burst length for Read and Write
operations
Programmable CAS Latency (3 clocks)
Programmable burst sequence: sequential or
interleaved
Burst concatenation and truncation supported
for maximum data throughput
Auto Pre-charge option for each Read or Write
burst
4096 refresh cycles every 64ms
Auto Refresh and Self Refresh Modes
Pre-charge Power Down and Active Power
Down Modes
Industrial Temperature Availability
Lead-free Availability
DD
and V
DDQ
): 2.6V
DEVICE OVERVIEW
ISSI’s 128-Mbit DDR SDRAM achieves high-speed data
transfer using pipeline architecture and two data word
accesses per clock cycle. The 134,217,728-bit memory
array is internally organized as four banks of 32M-bit to
allow concurrent operations. The pipeline allows Read
and Write burst accesses to be virtually continuous, with
the option to concatenate or truncate the bursts. The
programmable features of burst length, burst sequence
and CAS latency enable further advantages. The device
is available in 16-bit data word size. Input data is regis-
tered on the I/O pins on both edges of Data Strobe
signal(s), while output data is referenced to both edges of
Data Strobe and both edges of CLK. Commands are
registered on the positive edges of CLK. Auto Refresh,
Active Power Down, and Pre-charge Power Down modes
are enabled by using clock enable (CKE) and other
inputs in an industry-standard sequence. All input and
output voltage levels are compatible with SSTL 2.
IS43R16800A
1M x16x8 Banks
V
V
66-pin TSOP-II
DD
DDQ
: 2.6V
: 2.6V
PRELIMINARY INFORMATION
JULY 2005
ISSI
®
1

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IS42S32800B Summary of contents

Page 1

... Lead-free Availability Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — ...

Page 2

... COLUMN ADDRESS BUFFER 2 16) X REFRESH CONTROLLER SELF REFRESH CONTROLLER REFRESH COUNTER ROW ADDRESS 12 BUFFER 12 BANK CONTROL LOGIC Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI LDM, UDM DATA IN 2 BUFFER 16 16 I/O 0-15 UDQS, LDQS DDQ DATA OUT BUFFER ...

Page 3

... Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/ ...

Page 4

... RAS and CAS. See “Command Truth Table” for details. VDDQ is the output buffer power supply. VDD is the device power supply. VREF is the reference voltage for SSTL 2. VSSQ is the output buffer ground. VSS is the device ground. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00A 07/11/05 ...

Page 5

... DC execution of each differential input (DC) specifies the input differential voltage required for switching. ID for CLK or CLK > V for CLK or CLK < 0.18V REF IL Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 (1) Rating –1.0 to +3.6 –1.0 to +3.6 –1.0 to +3.6 Com +70 –55 to +125 Test Condition ...

Page 6

... IL Input V -0.2V; Input 0.2V DD Four bank interleaved Reads with Auto Precharge Address and Controls inputs change per Read, Write, or Active command; one bank with tRC = tRC (min) Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI = 2.6V 100 MHz) Min. Max. Unit ...

Page 7

... DAL t Refresh Interval Time REF Notes: 1. Operating outside the “Absolute Maximum Ratings” may lead to temporary or permanent device failure. 2. Power up sequence describe in “Initialization” section. 3. All voltages are referenced to Vss. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/ 2.6V +/- 0.1V +70 ...

Page 8

... For each of the add-ins, if not an integer already, round up to the nearest integer. DAL REF power supply variation per cycle expected to be less than 0.4V per 400 cycles. DD Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00A 07/11/05 ...

Page 9

... Mode Register Set command cycle time MRD t Self Refresh Exit to non-read command SNR t Self Refresh Exit to Read command SRD t Power Down Entry PDEN t Power Down Exit to command input PDEX Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Symbol Value V (AC 0.31 IH REF V (AC ...

Page 10

... JEDEC specification recommends that a DDR SDRAM receive another Load Mode Register command to clear the DLL, with NOP/Deselect commands for at least tMRD. The device is now ready to receive a valid command for normal operation. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® are TT Rev ...

Page 11

... Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 loaded only if all banks are idle. After the Load Mode Register command, a minimum time of tMRD must pass before the subsequent command is issued. CAS LATENCY After a Read command is issued to the device, a latency of several clock cycles is necessary prior to the validity of data on the data bus ...

Page 12

... M8 is set to 0. This device does not require it, but JEDEC specifications require that any time that the DLL is reset, it later be cleared prior for normal operation. Order of Accesses in a Burst Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Rev. 00A 07/11/05 ...

Page 13

... Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 DLL Enable/Disable When the Load Extended Mode Register command is issued, DLL should be enabled (E0 = 0). Normal operation of the device requires this, but DLL can be disabled for debugging or evaluation, if necessary. ...

Page 14

... Active command is issued. Burst Terminate (BST) The Burst Terminate command truncates the burst of the most recently issued Read command (with Auto Pre-charge disabled). The open row being accessed in the Read burst remains open. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00A 07/11/05 ...

Page 15

... WE are High. The values on the inputs BA0 and BA1 specify the bank to access, and the address inputs specify the starting column in the open row. If Auto Pre-charge is enabled in the Read command, the Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 open row will be pre-charged after completion of the Read burst ...

Page 16

... A10 is High, BA0 and BA1 are Don’t Care. Once any bank has been pre- charged, it becomes idle. Before any row can have a Read or Write access, it must be activated. Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00A ...

Page 17

... Power down exit (PDEX) Remark: H: VIH. L: VIL. ×: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 CKE CS CS RAS ...

Page 18

... NOP H L BST L H BA, CA, A10 READ/READA L L BA, CA, A10 WRIT/WRITA H H BA, RA ACT H L BA, A10 PRE, PALL L Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI Operation Next state NOP ldle NOP ldle 11 ILLEGAL* — 11 ILLEGAL* — 11 ILLEGAL* — 11 ILLEGAL* — NOP ...

Page 19

... L 9 Write recovering Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Address Command DESL H NOP L BST H BA, CA, A10 READ/READA L BA, CA, A10 WRIT/WRITA H BA, RA ACT L BA, A10 PRE, PALL DESL H NOP ...

Page 20

... BA, CA, A10 WRIT/WRIT BA, RA ACT H L BA, A10 PRE, PALL L Minimum delay (Concurrent AP supported) BL/2 CL(rounded up)+ (BL/ (BL/2) + tWTR BL/2 1 Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI Operation Next state NOP Precharging NOP Precharging ILLEGAL — 14 ILLEGAL* — 14 ILLEGAL* — 11, 14 ILLEGAL* — 11, 14 ILLEGAL* — ...

Page 21

... L Remark: H: VIH. L: VIL. : VIH or VIL Note: Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 /RAS /CAS /WE Address Operation ...

Page 22

... CKE ROW ACTIVE BST WRITE READ WRITE READ WITH WITH AP AP WRITE READ READ READ WITH AP WRITE READ WITH AP WITH AP PRECHARGE WRITEA READA PRECHARGE PRECHARGE POWER PRECHARGE ON PRECHARGE Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI SELF *1 AUTO Read ® Rev. 00A 07/11/05 ...

Page 23

... CK /CK tRCD Command NOP ACT NOP Address Row DQS Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/ READ NOP Column tRPRE out0 out1 out0 out1 out2 out3 out0 out1 out2 out3 out4 out5 out6 out7 Read Operation (Burst Length) ...

Page 24

... Read Operation (/CAS Latency) tn tn+0.5 tn+1 tn+2 tRCD NOP WRITE Column tWPRE tWPRES in0 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 Write Operation Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI t3.5 t4 t4.5 t5 t5.5 tRPST VTT VTT out1 out2 out3 tn+3 tn+4 tn+5 NOP in4 in5 in6 in7 BL: Burst length ® ...

Page 25

... High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed /CK READ Command DQS Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 BST ...

Page 26

... BL/2) READA NOP tAC,tDQSCK out0 ". Read with auto-precharge tRAS (min) WRITA NOP BL cycles in1 in2 in3 in4 ". Burst Write ( Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI tRP (min) ACT out1 out2 out3 tRP ACT Rev. 00A ® 07/11/05 ...

Page 27

... BA DQ DQS Bank0 Active READ to READ Command Interval (same ROW address in the same bank) Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Operation The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘ ...

Page 28

... READ READ ACT NOP Row1 Column A Column B Column = A Read Bank3 Bank0 Bank3 Active Read Read READ to READ Command Interval (different bank) Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI t10 NOP out out out out out out ...

Page 29

... BA DQ DQS Bank0 Active WRITE to WRITE Command Interval (same ROW address in the same bank) Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Operation The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...

Page 30

... Bank0 Active tn+1 ACT NOP WRIT WRIT Row1 Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Bank0 Write Bank3 Active WRITE to WRITE Command Interval (different bank) Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI tn+2 tn+3 tn+4 tn+5 NOP Bank3 Write Bank0, 3 ® Rev. 00A 07/11/05 ...

Page 31

... READ BST DM DQ High-Z DQS Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Operation Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘ ...

Page 32

... ACT command. tRCD after the ACT command, the consecutive read command can be issued NOP READ tWRD (min) tWTR* BL cycle in1 in2 in3 INPUT WRITE to READ Command Interval Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI NOP out0 out1 out2 OUTPUT ® Rev. 00A ...

Page 33

... DM DQ in0 DQS Data masked Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Operation DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command not necessary. ...

Page 34

... Data masked [WRITE to READ delay = 2 clock cycle NOP READ 3 cycle CL=3 tWTR* in1 in2 in3 Data masked [WRITE to READ delay = 3 clock cycle] Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI NOP High-Z out0 out1 out2 out3 High ...

Page 35

... A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP (= CL) after the precharge command /CK Command NOP DQ DQS READ to PRECHARGE Command Interval (same bank): To stop output data ( Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/ PRE/ NOP PALL out0 out1 out2 out3 ...

Page 36

... Precharge Termination in Write Cycles (same bank) ( NOP tWPD in0 in1 in2 in3 Last data input NOP tWR in0 in1 in2 in3 Data masked Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI PRE/PALL NOP tWR PRE/PALL NOP ® Rev. 00A 07/11/05 ...

Page 37

... The interval between setting the mode register and executing a bank-active command must be no less than tMRD. CK /CK Command Address Mode Register Set Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. ...

Page 38

... By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function DQS Mask Mask Write mask latency = 0 DM Control Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI ® Rev. 00A 07/11/05 ...

Page 39

... CK tCH tRPRE DQS DQ (Dout) Write Timing Definition tCK /CK CK tDQSS DQS tWPRES tWPRE DQ (Din) DM Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 tIS tIH tIH tIS tCL tDQSCK tDQSCK tDQSCK tDQSQ tQH tLZ tAC tAC tQH tDSS tDQSL tDQSH ...

Page 40

... Bank 0 Bank 0 Bank 0 Read Read Precharge Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tRPST ...

Page 41

... BA tIS tIH A10 tIS tIH Address DQS (input (input) Bank 0 Bank 0 Active Active Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 tRC tRAS tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tDQSS tDQSL ...

Page 42

... tMRD Bank 3 Mode Bank 3 Read register Active set C:a R:b C:b a tRWD Bank 0 Bank 3 Bank 3 Read Active Write Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI Bank Precharge VIH or VIL C:b'' b’’ b tWRD Bank 3 Read Read cycle ...

Page 43

... Auto Refresh Cycle /CK CK VIH CKE /CS /RAS /CAS /WE BA Address A10=1 DM DQS DQ (output) DQ (input) tRP Precharge If needed Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 High-Z tRFC Auto Bank 0 Refresh Active ISSI Bank 0 Read VIH or VIL ® ...

Page 44

... BA Address A10=1 DM DQS DQ (output) DQ (input) Precharge If needed 44 tIS tIH CKE = low High-Z tRP Self Self refresh refresh exit entry Integrated Silicon Solution, Inc. — 1-800-379-4774 ISSI tSNR tSRD Bank 0 Bank 0 Active Read VIH or VIL ® Rev. 00A 07/11/05 ...

Page 45

... IS43R16800A ORDERING INFORMATION Commercial Range: 0°C to +70°C Frequency Speed (ns) 400 MHz 5 400 MHz 5 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. 00A 07/11/05 Order Part No. Package IS43R16800A-5T 66-pin TSOP-II IS43R16800A-5TL 66-pin TSOP-II, Lead-free ISSI ® 45 ...

Page 46

... C 0.12 0.21 D 22.02 22.42 E1 10.03 10.29 E 11.56 11.96 e 0.65 BSC L 0.40 0.60 L1 — — ZD 0.71 REF 0° 8° Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. A 08/09/05 N/2 Inches Min Max — 0.047 0.002 0.006 — — 0.009 0.016 0.005 0.0083 0.867 0.8827 0.395 0.405 0.455 0.471 0.026 BSC 0.016 0.024 — ...

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