AD829JR Analog Devices Inc, AD829JR Datasheet - Page 12

• Manufacturer Part Number: AD829JR
• Description: IC VIDEO OPAMP LN HS 8-SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD829JR

• Slew Rate: 230 V/µs
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Applications: Voltage Feedback
• Number Of Circuits: 1
• -3db Bandwidth: 120MHz
• Current - Supply: 5.3mA
• Current - Output / Channel: 32mA
• Voltage - Supply, Single/dual (±): ±4.5 V ~ 18 V
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 600MHz
• No. Of Pins: 8
• Settling Time: 65ns
• Operating Temperature Max: 70°C
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD829
THEORY OF OPERATION
The AD829 is fabricated on the Analog Devices, Inc., proprietary
complementary bipolar (CB) process, which provides PNP and
NPN transistors with similar f
Figure 35, the AD829 input stage consists of an NPN differential
pair in which each transistor operates at a 600 μA collector current.
This gives the input devices a high transconductance, which in
turn gives the AD829 a low noise figure of 2 nV/√Hz at 1 kHz.
The input stage drives a folded cascode that consists of a fast pair of
PNP transistors. These PNPs drive a current mirror that provides a
differential-input-to-single-ended-output conversion. The high
speed PNPs are also used in the current-amplifying output stage,
which provides a high current gain of 40,000. Even under heavy
loading conditions, the high f
using the CB process, permit cascading two stages of emitter
followers while maintaining 60 phase margin at closed-loop
bandwidths greater than 50 MHz.
Two stages of complementary emitter followers also effectively
buffer the high impedance compensation node (at the C
from the output so that the AD829 can maintain a high dc open-
loop gain, even into low load impedances (92 dB into a 150 Ω
load and 100 dB into a 1 kΩ load). Laser trimming and PTAT
biasing ensure low offset voltage and low offset voltage drift,
enabling the user to eliminate ac coupling in many applications.
For added flexibility, the AD829 provides access to the internal
frequency compensation node. This allows users to customize the
frequency response characteristics for a particular application.
Unity-gain stability requires a compensation capacitance of 68 pF
(Pin 5 to ground), which yields a small signal bandwidth of
66 MHz and slew rate of 16 V/μs. The slew rate and gain
bandwidth product varies inversely with compensation
capacitance. Table 4 and Figure 37 show the optimum
compensation capacitance and the resulting slew rate for
a desired noise gain.
+IN
1.2mA
–IN
OFFSET NULL
Figure 35. Simplified Schematic
T
s of the NPN and PNPs, produced
T
s of 600 MHz. As shown in
C
COMP
12.5pF
C
500Ω
R
15Ω
15Ω
COMP
+V
OUTPUT
–V
pin)
S
S
Rev. H | Page 12 of 20
For gains between 1 and 20, choose C
bandwidth relatively constant. The minimum gain that will still
provide stability depends on the value of the external
compensation capacitance.
An RC network in the output stage (see Figure 35) completely
removes the effect of capacitive loading when the amplifier
compensates for closed-loop gains of 10 or higher. At low
frequencies, and with low capacitive loads, the gain from the
compensation node to the output is very close to unity. In this case,
C is bootstrapped and does not contribute to the compensation
capacitance of the device. As the capacitive load increases, a pole
forms with the output impedance of the output stage, which
reduces the gain, and subsequently, C is incompletely bootstrapped.
Therefore, some fraction of C contributes to the compensation
capacitance, and the unity-gain bandwidth falls. As the load
capacitance is further increased, the bandwidth continues to fall,
and the amplifier remains stable.
EXTERNALLY COMPENSATING THE AD829
The AD829 is stable with no external compensation for noise
gains greater than 20. For lower gains, two different methods of
frequency compensating the amplifier can be used to achieve
closed-loop stability: shunt and current feedback compensation.
SHUNT COMPENSATION
Figure 36 and Figure 37 show that shunt compensation has an
external compensation capacitor, C
compensation pin and ground. This external capacitor is tied in
parallel with approximately 3 pF of internal capacitance at the
compensation node. In addition, a small capacitance, C
parallel with resistor R2, compensates for the capacitance at the
inverting input of the amplifier.
Figure 36. Inverting Amplifier Connection Using External Shunt
V
IN
CABLE
COAX
50Ω
50Ω
R1
Compensation
2
3
AD829
–
+
–V
4
C
S
+V
LEAD
R2
7
COMP
COMP
S
0.1μF
5
, connected between the
C
to keep the small signal
COMP
0.1μF
6
1kΩ
V
OUT
LEAD
, in