SST49LF080A-33-4C-WH Silicon Storage Technology, Inc, SST49LF080A-33-4C-WH Datasheet
SST49LF080A-33-4C-WH
Available stocks
Related parts for SST49LF080A-33-4C-WH
SST49LF080A-33-4C-WH Summary of contents
Page 1
... Erase and Program time increase with accumulated Erase/Program cycles. To meet high density, surface mount requirements, the SST49LF080A device is offered in 32-lead TSOP and 32- lead PLCC packages. See Figures 1 and 2 for pin assign- ments and Table 1 for pin descriptions. ...
Page 2
... TBL#, WP INIT#, RST System Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Response To Invalid Fields Abort Mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Data# Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Toggle Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Multiple Device Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Registers General Purpose Inputs Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 JEDEC ID Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ©2003 Silicon Storage Technology, Inc. 8 Mbit LPC Flash 2 SST49LF080A S71235-00-000 4/03 ...
Page 3
... Mbit LPC Flash SST49LF080A PARALLEL PROGRAMMING MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Reset Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Byte-Program Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Sector-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Block-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chip-Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Write Operation Status Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data# Polling ( Toggle Bit ( Data Protection (PP Mode Hardware Data Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Software Data Protection (SDP SOFTWARE COMMAND SEQUENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ELECTRICAL SPECIFICATIONS ...
Page 4
... FIGURE 32: Software Product ID Command Sequences Flowchart (LPC Mode FIGURE 33: Byte-Program Command Sequences Flowchart (PP Mode FIGURE 34: Wait Options Flowchart (PP Mode FIGURE 35: Software Product ID Command Sequences Flowchart (PP Mode FIGURE 36: Erase Command Sequence Flowchart (PP Mode ©2003 Silicon Storage Technology, Inc. 8 Mbit LPC Flash 4 SST49LF080A S71235-00-000 4/03 ...
Page 5
... TABLE 5: LPC Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TABLE 6: LPC Write Cycle TABLE 7: Multiple Device Selection Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 TABLE 8: General Purpose Inputs Register TABLE 9: Memory Map Register Addresses for SST49LF080A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 TABLE 10: Operation Modes Selection (PP Mode TABLE 11: Software Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TABLE 12: DC Operating Characteristics (All Interfaces TABLE 13: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TABLE 14: Pin Capacitance ...
Page 6
... IAGRAM TBL# WP# INIT# LAD[3:0] LCLK LPC LFRAME# Interface ID[3:0] GPI[4:0] R/C# A[10:0] Programmer DQ[7:0] Interface OE# WE# ©2003 Silicon Storage Technology, Inc. X-Decoder Address Buffers & Latches Control Logic MODE RST# CE Mbit LPC Flash SST49LF080A SuperFlash Memory Y-Decoder I/O Buffers and Data Latches 1235 B1.0 S71235-00-000 4/03 ...
Page 7
... Mbit LPC Flash SST49LF080A PIN ASSIGNMENTS A6 (GPI0) A5 (WP#) A4 (TBL#) DQ0 (LAD0) FIGURE SSIGNMENTS FOR (CE#) 4 MODE (MODE) 5 A10 (GPI4) 6 R/C# (LCLK RST# (RST (GPI3 (GPI2 (GPI1 (GPI0 (WP#) ...
Page 8
... This signal must be asserted to select the device. When CE# is low, the device is enabled. When CE# is high, the device is placed in low power standby mode Unconnected pins Mbit LPC Flash SST49LF080A ) for PP mode and low (V ) for LPC mode T1.0 1235 S71235-00-000 ...
Page 9
... Mbit LPC Flash SST49LF080A DEVICE MEMORY MAPS TBL# WP# for Block 0~14 FIGURE EVICE EMORY ©2003 Silicon Storage Technology, Inc. 0FFFFFH Block 15 0F0000H 0EFFFFH Block 14 0E0000H 0DFFFFH Block 13 0D0000H 0CFFFFH Block 12 0C0000H 0BFFFFH Block 11 0B0000H 0AFFFFH Block 10 0A0000H 09FFFFH Block 9 090000H ...
Page 10
... CE# must be asserted one cycle before the start cycle to select the SST49LF080A for Read and Write operations. Once the SST49LF080A identifies the operation as valid (a start value of all zeros), it next expects a nibble that indi- cates whether this is a memory Read or Write cycle. Once this is received, the device is now ready for the Address cycles ...
Page 11
... Device #0 Memory Access 1. For device #0 (Boot Device), SST49LF080A decodes the physical addresses of the top 2 blocks (including Boot Block) both at system memory ranges FFFF FFFFH to FFFE 0000H and 000F FFFFH to 000E 0000H. ©2003 Silicon Storage Technology, Inc. Both TBL# and WP# pins must be set to their required pro- tection states prior to starting a Program or Erase opera- tion ...
Page 12
... In this clock cycle, the host has driven the bus to all 1s and then then Float floats the bus. This is the first part of the bus “turnaround cycle.” Float The SST49LF080A takes control of the bus during this cycle then OUT OUT The SST49LF080A outputs the value 0000b indicating that data will be available during the next clock cycle ...
Page 13
... The SST49LF080A outputs the values 0000, indicat- ing that it has received data or a flash command. 1111 OUT then Float In this clock cycle, the SST49LF080A has driven the bus to all ‘1’s and then floats the bus. This is the first part of the bus “turnaround cycle.” Float then IN Host resumes control of the bus during this cycle ...
Page 14
... If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Data# Polling When the SST49LF080A device is in the internal Program operation, any attempt to read D[7] will produce the com- plement of the true data. Once the Program operation is completed, D[7] will produce true data ...
Page 15
... are used to select the device with proper IDs. See Table 7 for IDs. The SST49LF080A will compare these bits with ID[3:0]’s strapping values. If there is a mis- match, the device will ignore the remainder of the cycle. TABLE ULTIPLE ...
Page 16
... General Purpose Inputs Register The GPI_REG (General Purpose Inputs Register) passes the state of GPI[4:0] pins at power-up on the SST49LF080A recommended that the GPI[4:0] pins be in the desired state before LFRAME# is brought low for the beginning of the next bus cycle, and remain in that state until the end of the cycle ...
Page 17
... SST49LF080A. See Table 23 for Reset timing parameters and Figure 16 for Reset timing diagram. Read The Read operation of the SST49LF080A device is con- trolled by OE#. OE# is the output control and is used to gate data from the output pins. Refer to the Read cycle tim- ing diagram, Figure 17, for further details. ...
Page 18
... If both reads are valid, then the device has completed the Write cycle, otherwise the rejec- tion is valid. Data# Polling ( When the SST49LF080A device is in the internal Program operation, any attempt to read DQ will produce the com- 7 plement of the true data. Once the Program operation is completed, DQ will produce true data ...
Page 19
... Silicon Storage Technology, Inc. Software Data Protection (SDP) The SST49LF080A provides the JEDEC approved Soft- ware Data Protection scheme for all data alteration opera- tion, i.e., Program and Erase. Any Program operation requires the inclusion of a series of three-byte sequence. ...
Page 20
... Sector-Erase Address for Block-Erase Address X 6. Chip-Erase is supported in PP mode only 7. SST Manufacturer’ BFH, is read with A With SST49LF080A Device ID = 5BH, is read with Both Software ID Exit operations are equivalent ©2003 Silicon Storage Technology, Inc. S EQUENCE 1 1 2nd ...
Page 21
... Mbit LPC Flash SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# 3rd Start LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write ...
Page 22
... TAR A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b Load Address in 8 Clocks 2 Clocks When internal write complete, the DQ 7 will equal to D7. S (LPC M ) EQUENCE ODE 22 8 Mbit LPC Flash SST49LF080A Start next Data TAR Sync Command 0000b TAR Dn[7:4] 1111b Tri-State 0000b 1 Clock 2 Clocks 1 Clock Next start Sync ...
Page 23
... Mbit LPC Flash SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Read Start Cycle LAD[3:0] 0000b 010Xb A[31:28] A[27:24] 1 Clock 1 Clock Note: 1. Address must be within memory address range specified in Table 4. ...
Page 24
... Load Sector Address in 8 Clocks Load Data “30” Clocks Write the 6th command (target sector to be erased) to the device in LPC mode Sector Address S (LPC M ) EQUENCE ODE 24 8 Mbit LPC Flash SST49LF080A Start next Command Data TAR Sync TAR 1010b 1111b Tri-State 0000b ...
Page 25
... Mbit LPC Flash SST49LF080A CE# LCLK LFRAME# Memory Write 1st Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 2nd Start Cycle 0000b 011Xb LAD[3:0] 1 Clock 1 Clock CE# LCLK LFRAME# Memory Write 3rd Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock CE# ...
Page 26
... EADOUT ©2003 Silicon Storage Technology, Inc. Address 1 A[31:28] A[27:24] A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] Load Address in 8 Clocks C S (LPC M OMMAND EQUENCE ODE 26 8 Mbit LPC Flash SST49LF080A TAR Sync Data TAR 1111b Tri-State 0000b D[3:0] D[7:4] 2 Clocks 1 Clock Data out 2 Clocks 1235 F11.0 ) S71235-00-000 Start next 0000b 1 Clock ...
Page 27
... Mbit LPC Flash SST49LF080A ELECTRICAL SPECIFICATIONS The AC and DC specifications for the LPC interface signals (LA0[3:0], LFRAME, LCLCK and RST#) as defined in Section 4.2.2.4 of the PCI local Bus specification, Rev. 2.1. Refer to Table 12 for the DC voltage and current speci- fications. Refer to Tables 16 through 19 and Tables 21 through 23 for the AC timing specifications for Clock, Read, Write, and Reset operations. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “ ...
Page 28
... V I =-500 µ min, LFRAME IH OWER UP IMINGS =3.3V, Ta=25 °C, f=1 Mhz, other pins open Mbit LPC Flash SST49LF080A and Address Input =V (PP mode) (PP Mode) TRC min Max and Address Input =V (PP mode) (PP Mode) TRC min , f=33 MHz, CE#=0 ...
Page 29
... Mbit LPC Flash SST49LF080A TABLE 15 ELIABILITY HARACTERISTICS Symbol Parameter 1 N Endurance END 1 T Data Retention Latch Up LTH 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 16 LOCK IMING ...
Page 30
... V =3.0-3.6V (LPC M ) ODE reset procedure is performed during a Program or Erase operation. RSTE T PRST T KRST T RSTP T RSTF (LPC M ) ODE 30 8 Mbit LPC Flash SST49LF080A Min Max Units 1 ms 100 µs 100 µs 10 µs T17.0 1235 Sector-/Block-Erase T RSTE or Program operation ...
Page 31
... Mbit LPC Flash SST49LF080A AC Characteristics TABLE 18 EAD RITE YCLE Symbol Parameter T Clock Cycle Time CYC T Data Set Up Time to Clock Rising SU T Clock Rising to Data Hold Time Clock Rising to Data Valid VAL T Byte Programming Time BP T Sector-Erase Time SE T Block-Erase Time ...
Page 32
... M ONDITION ARAMETERS Value overdrive over V and V . Timing parameters must be met with no more over Mbit LPC Flash SST49LF080A 1235 F14 TEST MAX 1235 F15.0 ) ODE Units V/ns T20.0 1235 ...
Page 33
... Mbit LPC Flash SST49LF080A TABLE 21 EAD YCLE IMING Symbol Parameter T Read Cycle Time RC T RST# High to Row Address Setup RST T R/C# Address Set-up Time AS T R/C# Address Hold Time AH T Address Access Time AA T Output Enable Access Time OE T OE# Low to Active Output ...
Page 34
... Row Address Column Address OLZ D ( IAGRAM ODE 34 8 Mbit LPC Flash SST49LF080A Row Address T RSTP Sector-/Block-Erase T RSTE or Program operation aborted T RSTC Chip-Erase aborted T RST 1235 F16.0 Row Address Column Address OHZ High-Z Data Valid 1235 F17 ...
Page 35
... Mbit LPC Flash SST49LF080A T RST RST# Row Address Addresses T AS R/C# OE# WE# DQ 7-0 FIGURE 18 RITE YCLE IMING Addresses Row R/C# WE# OE FIGURE 19 ATA OLLING IMING ©2003 Silicon Storage Technology, Inc. Column Address CWH T OES ...
Page 36
... BA = Byte-Program Address A = Most Significant Address MS FIGURE 21 YTE ROGRAM IMING ©2003 Silicon Storage Technology, Inc. T OET D ( IAGRAM ODE 2AAA 5555 ( IAGRAM ODE 36 8 Mbit LPC Flash SST49LF080A D 1235 F20.0 BA Internal Program Starts DATA 1235 F21.0 S71235-00-000 4/03 ...
Page 37
... Mbit LPC Flash SST49LF080A A 14-0 (Internal A ) 5555 MS-0 R/C# OE Sector Address X FIGURE 22 ECTOR RASE IMING A 14-0 (Internal A ) 5555 MS-0 R/C# OE Block Address X FIGURE 23 LOCK RASE IMING ©2003 Silicon Storage Technology, Inc. 2AAA 5555 5555 ( IAGRAM ODE 2AAA ...
Page 38
... OE# WE 7-0 FIGURE 24 HIP RASE IMING A 14-0 (Internal A ) 5555 MS-0 R/ 7-0 Note: Device ID = 5BH for SST49LF080A FIGURE 25 OFTWARE NTRY AND ©2003 Silicon Storage Technology, Inc. 2AAA 5555 5555 ( IAGRAM ODE 2AAA 5555 T WPH ( ...
Page 39
... Mbit LPC Flash SST49LF080A A 14-0 (Internal A ) MS-0 R/C# OE# WE# DQ 7-0 FIGURE 26 OFTWARE XIT V IHT INPUT V ILT AC test inputs are driven at V (0.9 V IHT points for inputs and outputs are V FIGURE 27 NPUT UTPUT TO DUT FIGURE 28 EST OAD XAMPLE ©2003 Silicon Storage Technology, Inc. ...
Page 40
... Address: 5555H Write Data: AAH Cycle: 1 Address: 2AAAH Write Data: 55H Cycle: 2 Address: 5555H Write Data: A0H Cycle: 3 Address: A Write Data: D Cycle: 4 Wait T BP Available for Next Byte 1235 F30.0 FIGURE 30 YTE ROGRAM (LPC M ) ODE 40 SST49LF080A LOWCHART S71235-00-000 4/03 ...
Page 41
... Mbit LPC Flash SST49LF080A Command Sequence Address: 2AAAH Address: 2AAAH FIGURE 31 RASE OMMAND ©2003 Silicon Storage Technology, Inc. Block-Erase Sector-Erase Command Sequence Address: 5555H Address: 5555H Write Data: AAH Write Data: AAH Cycle: 1 Cycle: 1 Address: 2AAAH Write Data: 55H ...
Page 42
... IDA Available for Next Command Note: X can but no other value OMMAND EQUENCES LOWCHART 42 8 Mbit LPC Flash SST49LF080A Address: XXXXH Write Data: F0H Cycle: 1 Wait T IDA Available for Next Command 1235 F32.0 (LPC M ) ODE S71235-00-000 ...
Page 43
... Mbit LPC Flash SST49LF080A FIGURE 33 YTE ROGRAM OMMAND ©2003 Silicon Storage Technology, Inc. Start Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: A0H Address: 5555H Load Byte Address/Byte Data Wait for end of Program ( Data# Polling ...
Page 44
... Silicon Storage Technology, Inc. Toggle Bit Byte- Program/Erase Initiated Read byte Read same No byte No Does DQ 6 match? Yes Program/Erase Completed ( ODE 44 8 Mbit LPC Flash SST49LF080A Data# Polling Byte- Program/Erase Initiated Read true data? Yes Program/Erase Completed 1235 F34.0 S71235-00-000 4/03 ...
Page 45
... Mbit LPC Flash SST49LF080A Software Product ID Entry Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 90H Address: 5555H Wait T IDA Read Software ID FIGURE 35 OFTWARE RODUCT ©2003 Silicon Storage Technology, Inc. Software Product ID Exit Command Sequence ...
Page 46
... Wait T BE Block erased to FFH F ( EQUENCE LOWCHART ODE 46 8 Mbit LPC Flash SST49LF080A Sector-Erase Command Sequence Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH Write data: 80H Address: 5555H Write data: AAH Address: 5555H Write data: 55H Address: 2AAAH ...
Page 47
... XX Valid combinations for SST49LF080A SST49LF080A-33-4C-WH SST49LF080A-33-4C-NH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. Non-Pb: All devices in this data sheet are also offered in non-Pb (no lead added) packages. ...
Page 48
... SIDE VIEW .112 .106 .029 .020 R. .040 x 30˚ .023 .030 MAX. .021 .013 .400 .032 BSC .026 .050 BSC .015 Min. .095 .075 .140 .125 (PLCC Mbit LPC Flash SST49LF080A BOTTOM VIEW R. .530 .490 .032 .026 32-plcc-NH-3 S71235-00-000 4/03 ...
Page 49
... ODE TABLE 24 EVISION ISTORY Number 00 • Initial release (SST49LF080A previously released in data sheet S71206) Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 ©2003 Silicon Storage Technology, Inc. 8.10 7.90 1.20 max. (TSOP ACKAGE ...