IC41LV44002A-50T INTEGRATED CIRCUIT SOLUTION, IC41LV44002A-50T Datasheet
IC41LV44002A-50T
Available stocks
Related parts for IC41LV44002A-50T
IC41LV44002A-50T Summary of contents
Page 1
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) Document Title 4Mx4 bit Dynamic RAM with EDO Page Mode Revision History Revision No History 0A Initial Draft The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. ...
Page 2
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS( (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE FEATURES • Extended Data-Out (EDO) Page Mode access cycle • TTL compatible inputs and outputs • Refresh Interval: -- 2,048 cycles/32 ms • Refresh Mode: RAS-Only, CAS-before-RAS (CBR), and Hidden • JEDEC standard pinout • ...
Page 3
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) FUNCTIONAL BLOCK DIAGRAM OE WE CAS CAS CONTROL LOGIC RAS RAS CLOCK GENERATOR REFRESH COUNTER ADDRESS BUFFERS A0-A10 TRUTH TABLE Function Standby Read Write: Word (Early Write) Read-Write EDO Page-Mode Read 1st Cycle: 2nd Cycle: EDO Page-Mode Write 1st Cycle: ...
Page 4
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) Functional Description The IC41C44002A and IC41LV44002A are CMOS DRAMs optimized for high-speed bandwidth, low power applications. During READ or WRITE cycles, each bit is uniquely addressed through the 11 address bits. These are entered 11 bits (A0-A10 time for the 2K refresh device ...
Page 5
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Voltage on Any Pin Relative to GND T V Supply Voltage CC I Output Current OUT P Power Dissipation D T Commercial Operation Temperature A T Storage Temperature STG Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
Page 6
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) ELECTRICAL CHARACTERISTICS (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter I Input Leakage Current IL I Output Leakage Current IO V Output High Voltage Level OH V Output Low Voltage Level OL I Standby Current: TTL Standby Current: CMOS Operating Current ...
Page 7
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) AC CHARACTERISTICS (1,2,3,4,5,6) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter t Random READ or WRITE Cycle Time RC Access Time from RAS t RAC Access Time from CAS t CAC t Access Time from Column-Address AA RAS Pulse Width t RAS RAS Precharge Time t RP CAS Pulse Width ...
Page 8
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) AC CHARACTERISTICS (Continued) (Recommended Operating Conditions unless otherwise noted.) Symbol Parameter OE Hold Time from WE during t OEH READ-MODIFY-WRITE cycle t Data-In Setup Time (15, 22 Data-In Hold Time (15, 22 READ-MODIFY-WRITE Cycle Time RWC RAS to WE Delay Time during t RWD READ-MODIFY-WRITE Cycle ...
Page 9
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) Notes initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS-Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the (MIN) and V (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V ...
Page 10
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) READ CYCLE RAS t CRP CAS t ASR ADDRESS Row WE I/O OE Note: is referenced from rising edge of RAS or CAS, whichever occurs last OFF RAS t CSH t RSH t t CAS RCD t t RAD RAL t t RAH ASC Column t RCS RAC ...
Page 11
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) EARLY WRITE CYCLE (OE = DON'T CARE) RAS t CRP CAS t ASR ADDRESS Row WE I/O Integrated Circuit Solution Inc. DR026-0A 09/04/2001 RAS t CSH t RSH t t CAS RCD t t RAD RAL RAH ASC CAH Column t CWL t RWL t t WCS WCH ...
Page 12
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles) RAS t CRP CAS t ASR ADDRESS Row WE I RWC t RAS t CSH t RCD t RAD RAH CAH ASC Column t RWD t t CWD RCS t AWD RAC t CAC t CLZ Open Valid ...
Page 13
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) EDO-PAGE-MODE READ CYCLE RAS t CRP CAS t RAD t ASR ADDRESS Row t RAH WE Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Both measurements must meet the t specifications. PC Integrated Circuit Solution Inc. ...
Page 14
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) EDO-PAGE-MODE EARLY-WRITE CYCLE RAS t CRP CAS t RAD t ASR ADDRESS Row t RAH RASP t CSH RCD CAS ASC CAH ASC Column Column t t CWL CWL t t WCS WCS t t WCH WCH ...
Page 15
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) EDO-PAGE-MODE READ-WRITE CYCLE RAS t CSH t t CRP RCD CAS t t ASR RAD t t ASC RAH ADDRESS Row t RWD t RCS WE t RAC t CAC t CLZ Open I/O OE Note: can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS for LATE WRITE only ...
Page 16
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) EDO-PAGE-MODE READ-EARLY-WRITE CYCLE RAS t CSH t t CRP RCD CAS t t ASR RAD t t ASC RAH ADDRESS Row t RCS WE t RAC t CAC Open I (Psuedo READ-MODIFY WRITE) t RASP CAS CP CAS CAH ASC CAH Column (A) Column ( ...
Page 17
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) AC WAVEFORMS READ CYCLE (With WE-Controlled Disable) RAS t CRP CAS t ASR ADDRESS Row WE I/O OE RAS RAS RAS RAS RAS-ONLY REFRESH CYCLE RAS t CRP CAS t ASR ADDRESS Row I/O Integrated Circuit Solution Inc. DR026-0A 09/04/2001 t CSH t t RCD CAS t RAD RAH ...
Page 18
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) CBR REFRESH CYCLE (Addresses DON'T CARE, WE=HIGH RAS t t RPC CHR t CP CAS I/O HIDDEN REFRESH CYCLE RAS t CRP CAS t ASR ADDRESS Row I/O OE Notes Hidden Refresh may also be performed after a Write Cycle. In this case LOW and OE = HIGH. is referenced from rising edge of RAS or CAS, whichever occurs last. ...
Page 19
... IC41C44002A/IC41C44002AS(L) IC41LV44002A/IC41LV44002AS(L) SELF REFRESH CYCLE (Addresses : WE and OE = DON'T CARE RAS CHD RPC CAS TIMING PARAMETERS -50 Symbol Min CHD CSR t 100 RASS RPS t 5 RPC Integrated Circuit Solution Inc. ...
Page 20
... IC41C44002AS-50T 2K 300mil TSOP-2 IC41C44002ASL-50J 2K IC41C44002ASL-50T 2K 300mil TSOP-2 IC41C44002AS-60J 2K IC41C44002AS-60T 2K 300mil TSOP-2 IC41C44002ASL-60J 2K IC41C44002ASL-60T 2K 300mil TSOP-2 Order Part No. Refresh IC41LV44002A-50J 2K IC41LV44002A-50T 2K 300mil TSOP-2 IC41LV44002A-60J 2K IC41LV44002A-60T 2K 300mil TSOP-2 Order Part No. Refresh IC41LV44002AS-50J 2K IC41LV44002AS-50T 2K 300mil TSOP-2 IC41LV44002ASL-50J 2K IC41LV44002ASL-50T 2K 300mil TSOP-2 IC41LV44002AS-60J 2K IC41LV44002AS-60T 2K 300mil TSOP-2 ...