IC62LV51216LL-55T INTEGRATED CIRCUIT SOLUTION, IC62LV51216LL-55T Datasheet
IC62LV51216LL-55T
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IC62LV51216LL-55T Summary of contents
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... IC62LV51216L IC62LV51216LL Document Title 512 bit Low Voltage and Ultra Low Power CMOS Static RAM Revision History Revision No History 0A Initial Draft 0B 1. Add CE2 pin for 48 pin TF-BGA 2. Change for I 3. Change for I 4. Change for Revise typo for pin assignment H1 from NC to A18 2. Change Truth Table of LB/UB control,CE1 and CE2 to " ...
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... Output and Enable inputs, CE1, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access. The IC62LV51216L and IC62LV51216LL are packaged in the JEDEC standare 44-pin TSOP-2 and 48-pin 8*10mm TF-BGA. =3.0V, T =25°C ...
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... IC62LV51216L IC62LV51216LL PIN CONFIGURATIONS 44-Pin TSOP CE1 6 I/O0 7 I/O1 8 I/O2 9 I/O3 10 Vcc 11 GND 12 I/O4 13 I/O5 14 I/ A18 18 A17 19 A16 20 A15 21 A14 22 PIN DESCRIPTIONS A0-A18 Address Inputs I/O0-I/O15 Data Input/Output CE1 Chip Enable1 Input CE2 Chip Enable2 Input, BGA only ...
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... IC62LV51216L IC62LV51216LL OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial –40°C to +85°C ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Terminal Voltage with Respect to GND TERM T Temperature Under Bias BIAS V Vcc related to GND CC T Storage Temperature STG P Power Dissipation T Notes: 1 ...
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... IC62LV51216L IC62LV51216LL AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input Reference Level Output Reference Level Output Load AC TEST LOADS OUTPUT 100 pF Including jig and scope Figure 1 IC62LV51216L POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I Vcc Dynamic Operating ...
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... IC62LV51216L IC62LV51216LL IC62LV51216LL POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I Vcc Dynamic Operating Supply Current I OUT I TTL Standby Current (TTL Inputs CE1 = V I CMOS Standby Current (CMOS Inputs) CE1 V or CE2 0.2V other input = 0-V OR ULB Control ...
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... IC62LV51216L IC62LV51216LL AC TEST LOADS READ CYCLE NO.1 (1,2) (Address Controlled) ( ADDRESS D OUT PREVIOUS DATA VALID AC WAVEFORMS READ CYCLE NO. 2 (1,3) ( OE, Controlled ADDRESS OE CE1 CE2 LB LZB HIGH-Z D OUT Notes HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, UB Address is valid prior to or coincident with CE1 LOW and CE2 HIGH transitions. ...
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... IC62LV51216L IC62LV51216LL WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Write Cycle Time WC t CE1 Low and CE2 HIGH to Write End SCE t Address Setup Time to Write End AW t Address Hold from Write End HA t Address Setup Time SA t LB, UB Valid to End of Write PWB ...
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... IC62LV51216L IC62LV51216LL WRITE CYCLE NO. 2 (WE Controlled HIGH During Write Cycle) ADDRESS OE CE1 CE2 UB DATA UNDEFINED OUT D IN WRITE CYCLE NO. 3 (WE Controlled LOW During Write Cycle) ADDRESS OE LOW CE1 CE2 UB DATA UNDEFINED OUT D IN Integrated Circuit Solution Inc ...
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... IC62LV51216L IC62LV51216LL WRITE CYCLE NO Controlled) ADDRESS OE CE1 CE2 WE UB OUT DATA UNDEFINED D IN DATA RETENTION SWITCHING CHARACTERISTICS Symbol Parameter V Vcc for Data Retention DR I Data Retention Current DR t Data Retention Setup Time SDR t Recovery Time RDR Notes CE1 V -0 ...
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... IC62LV51216L IC62LV51216LL DATA RETENTION WAVEFORM V CC 1.65V 1. CE1 GND Integrated Circuit Solution Inc. LPSR014-0C 1/22/2003 (CE1 Controlled) t Data Retention Mode SDR CE1 RDR 11 ...
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... HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C. Package IC62LV51216L-55TI TSOP-2 IC62LV51216L-55BI 8*10mm TF-BGA IC62LV51216L-70TI TSOP-2 IC62LV51216L-70BI 8*10mm TF-BGA IC62LV51216L-100TI TSOP-2 IC62LV51216L-100BI 8*10mm TF-BGA Package IC62LV51216LL-55TI TSOP-2 IC62LV51216LL-55BI 8*10mm TF-BGA IC62LV51216LL-70TI TSOP-2 IC62LV51216LL-70BI 8*10mm TF-BGA IC62LV51216LL-100TI TSOP-2 IC62LV51216LL-100BI 8*10mm TF-BGA Integrated Circuit Solution Inc. HEADQUARTER: HSIN-CHU, TAIWAN, R.O.C. ...