IC42S16800-6TG INTEGRATED CIRCUIT SOLUTION, IC42S16800-6TG Datasheet
IC42S16800-6TG
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IC42S16800-6TG Summary of contents
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Document Title 4(2)M x 8(16) Bit x 4 Banks (128-MBIT) SDRAM Revision History Revision No History 0A Initial Draft 0B Corrected typo on PIN FUNCTIONS and revise DC OPERATING CONDITIONS 0C Append two parameters t and t and modify DC operating condition RP 0D 1.Obsolete speed grade -7H 2.Support Pb-free package 3.Modify typo in page 16,17 ...
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... ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc. 2 DESCRIPTION The IC42S81600 and IC42S16800 are high-speed 134,217,728-bit synchronous dynamic random- access memories, organized as 4,194,304 and 2,097,152 (word x bit x bank), respectively. ...
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... Pin Name Function CLK Master Clock CKE Clock Enable CS Chip Select RAS Row Address Strobe CAS Column Address Strobe WE Write Enable DQ0 ~ DQ15 Data I/O Integrated Circuit Solution Inc. DR023-0E 6/11/2004 54-Pin TSOP-2 (IC42S16800) 54 VSS 53 DQ7 52 VSSQ VDDQ DQ6 49 VDDQ DQ5 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L FUNCTIONAL BLOCK DIAGRAM CLK Clock Generator CKE Address Mode Register CS RAS CAS WE 4 Bank D Row Bank C Address Bank B Buffer & Refresh Counter Bank A Sense Amplifier Column Decoder & Column Latch Circuit Address Buffer & Burst Data Control Circuit Counter ...
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... AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. The row address is specified by A0-A11. The column address is specified by A0-A9 (IC42S81600) / A0-A8 (IC42S16800) Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Supply Voltage (with respect Supply Voltage for Output (with respect to V DDQ V Input Voltage (with respect Output Voltage O I Short circuit output current O P Power Dissipation ( D T Operating Temperature OPT ...
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... Self-Refresh Current 6 CC Notes (max) is specified at the output open condition Input signals are changed one time during 30ns. 3. Normal version: IC42S81600/IC42S16800 4. Low power version: IC42S81600L/IC42S16800L DC CHARACTERISTICS 3.3 ± 0.3V unless otherwise noted SSQ Parameter Input Leakage Current ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L AC TEST CONDITIONS ( 3.3 ± 0.3V DDQ SS Parameter AC input Levels ( Input timing reference level /Output timing reference level Input rise and fall time Output load condition Output Load Conditions V V DDQ DDQ V OUT Device Under Test unless otherwise noted) ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L AC ELECTRICAL CHARACTERISTICS ( 3.3 ± 0.3V DDQ SS Symbol Parameter t 3 CLK Cycle Time CLK to valid output delay ( CLK high pulse width CH t CLK low pulse width CL t CKE setup time CKE t CKE hold time ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Basic Features and Function Description Simplified State Diagram Mode Register Set Write (Write recovery) CKE WRITE WRITE SUSPEND CKE Write with Auto Precharge WRITE A CKE WRITE A SUSPEND CKE Precharge POWER ON 10 MRS REF IDLE CKE ROW ACTIVE CKE Read (write recovery) ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L COMMAND TRUTH TABLE Symbol Command DESL Device deselect NOP No operation MRS Mode register set ACT Bank activate READ Read READA Read with auto precharge WRIT Write WRITA Write with auto precharge PRE Precharge select bank PALL Precharge all banks ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L OPERATION COMMAND TABLE Current State Command Idle DESL NOP or BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Row Active DESL NOP or BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Read DESL NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS Write ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L OPERATION COMMAND TABLE Current State Command DESL Write with auto NOP precharge BST READ / READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Precharging NOP BST READ/READA WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Row activating NOP BST READ/READA WRIT/WRITA ACT PRE/PALL ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L OPERATION COMMAND TABLE Current State Command DESL Write NOP recovering BST with auto READ/READA precharge WRIT/WRITA ACT PRE/PALL REF/SELF MRS DESL Auto NOP/BST Refreshing READ/WRIT ACT/PRE/PALL REF/SELF/MRS Mode DESL register NOP setting BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS Notes: 1. All entries assume that CKE was active (High level) during the preceding clock cycle. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh (S.R.) INVALID, CLK (n - 1)would exit S.R. Self-Refresh Recovery Self-Refresh Recovery Illegal Illegal Maintain S.R. Self-Refresh Recovery Idle After t RC Idle After t RC Illegal Illegal Begin clock suspend next cycle Begin clock suspend next cycle ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Initiallization Before starting normal operation, the following power on sequence is necessary to prevent SDRAM from damged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high , DQN high and NOP condition at the inputs. 2. Maintain stable power, table clock , and NOP input conditions for a minimum of 200us ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L MODE REGISTER Integrated Circuit Solution Inc. DR023-0E 6/11/2004 LTMODE ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Burst Length and Sequence Burst of Two Starting Address (column address A0, binary Burst of Four Starting Address (column address A1 - A0, binary Burst of Eight Starting Address (column address A2 - A0, binary) 000 001 010 011 100 101 110 111 Full page burst is an extension of the above tables of sequential addressing, with the length being 512 (for 16M x 8) and 256 (for 8Mx16) ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Address Bits of Bank-Select and Precharge A10 A11 A12 A13 Row (Activate command) Row A10 A11 A12 A13 (Precharge command A10 A11 A12 A13 Co1. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Precharge The precharge command can be asserted anytime after t Soon after the precharge command is asserted, the precharge operation is performed and the synchronous DRAM enters the idle state after t (min.) is satisfied. The parameter t RP The earliest timing in a read cycle that a precharge command can be asserted without losing any data in the burst is as follows ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Auto Precharge During a read or write command cycle, A10 controls whether auto precharge is selected. If A10 is high in the read or write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically. In the write cycle, t (min.) must be satisfied before asserting the next activate command to the bank being precharged. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Write with Auto Precharge During a write cycle, the auto precharge starts at the timing that is equal to the value of t input to the device. WRITE with AUTO PRECHRGE T0 CLK Command CAS latency = 2 DQ Command CAS latency = 3 DQ Remark WRITA means WRITE with AUTO Precharge In summary, the auto precharge cycle begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Read / Write Command Interval Read to Read Command Interval During a read cycle when a new read command is asserted, it will be effective after the CAS latency, even if the previous read operation has not completed. READ will be interrupted by another READ. Each read command can be asserted in every clock without any restriction. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Write to Read Command Interval The write command to read command interval is also a minimum of 1 cycle. Only the write data before the read command will be written. The data bus must be Hi-Z at least one cycle prior to the first D WRITE to READ Command Interval ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L READ to WRITE Command Interval T0 CLK Command DQM DQ Hi CLK Command Read DQM DQ T0 CLK Command DQM DQ Integrated Circuit Solution Inc. DR023-0E 6/11/2004 Read Write cycle Read Q2 necessary CAS latency ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L BURST Termination There are two methods to terminate a burst operation other than using a read or a write command. One is the burst stop command and the other is the precharge command. BURST Stop Command During a read burst, when the burst stop command is issued, the burst read data are terminated and the data bus goes to high-impedance after the CAS latency from the burst stop command ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L PRECHARGE TERMINATION PRECHARGE TERMINATION in READ Cycle During READ cycle, the burst read operation is terminated by a precharge command. When the precharge command is issued, the burst read operation is terminated and precharge starts. The same bank can be activated again after t When CAS latency is 2, the read data will remain valid until one clock after the precharge command. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Precharge Termination in WRITE Cycle During WRITE cycle, the burst write operation is terminated by a precharge command. When the precharge command is issued, the burst write operation is terminated and precharge starts. The same bank can be activated again after t invalid data in. During WRITE cycle, the write data written prior to the precharge command will be correctly stored. However, invalid data may be written at the same clock as the precharge command ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Mode Register Set T0 T1 CLK CKE CS RAS CAS WE BS0,1 A10 ADD DQM Precharge Command All Banks Integrated Circuit Solution Inc. DR023-0E 6/11/2004 RSC Address Key t RP Mode Register Command Set Command T10 29 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L AC Parameters for Write Timing ( CLK CK2 CH t CKE CMS t CKS t CMH CS RAS CAS WE *BS0 A10 ADD DQM t RCD DQ t RRD ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L AC Parameters for Write Timing ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 CLK CK3 t CMS CKE t CKS t CMH CS RAS CAS WE *BS0 A10 ADD ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L AC Parameters for Read Timing ( CLK CK2 CKE t CKS CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ Activate Command Bank A BS1=”L”, Bank C,D = Idle CMS t CMH t RRD t RAS AC2 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L AC Parameters for Read Timing ( CLK CK3 t CKE CMS t CKS CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ Activate Command Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR023-0E 6/11/2004 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Power on Sequence and Auto Refresh (CBR CLK High level CKE is required CS RAS CAS WE BS0, 1 A10 ADD DQM High Level is Necessary t RP Hi-Z DQ Precharge 1st Auto Command Refresh Inputs All Banks Command must be stable for 200us T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Clock Suspension During Burst Read (Using CKE CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ Read Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Clock Suspension During Burst Read (Using CKE CLK t CK3 CKE CS RAS CAS WE *BS0 RAa A10 ADD RAa CAa DQM Hi-Z DQ Read Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Clock Suspension During Burst Write (Using CKE CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ DAa0 Clock Activate Suspended Command 1 Cycle Bank A Write Command Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Clock Suspension During Burst Write (Using CKE CLK t CK3 CKE CS RAS CAS WE *BS0 RAa A10 ADD CAa RAa DQM Hi-Z DQ DAa0 Activate Suspended Command Bank A Write Command Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Power Down Mode and Clock Mask CLK t CK2 t CKS CKE CS RAS CAS WE *BS0 A10 RAa RAa ADD RAa DQM Hi-Z DQ ACTIVE STANDBY Activate Command Bank A Power Down Power Down Mode Entry Mode Exit BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Auto Refresh (CBR CLK t CK2 CKE CS RAS CAS WE *BS0, 1 A10 ADD DQM t RP Hi-Z DQ Precharge CBR Refresh Command Command All Banks BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Self Refresh (Entry and Exit CLK CKE CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ All Banks Self refresh must be idle Entry BS1=”L”, Bank C,D = Idle Clock can be stopped at CKE=Low. If clock is stopped, it must be restarted/stable for 4 clock cycles before CKE=High Integrated Circuit Solution Inc ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Column Read (Page With Same Bank CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ Precharge Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Column Read (Page With Same Bank CLK t CK3 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ Activate Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Column Write (Page With Same Bank CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra ADD Ra Ca DQM Hi-Z DQ Da0 Da1 Write Activate Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Column Write (Page With Same Bank CLK t CK CKE CS RAS CAS WE *BS0 A10 Ra ADD Ca Ra DQM Hi-Z DQ Da0 Activate Write Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR023-0E 6/11/2004 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Row Read (Interleaving Banks CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 ADD t t AC2 RCD DQM Hi-Z DQ QBa0 Activate Read Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Row Read (Interleaving Banks CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 ADD t RCD DQM Hi-Z DQ Read Activate Command Command Bank B Bank B BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR023-0E 6/11/2004 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Row Write (Interleaving Banks CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 ADD t DQM RCD Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 QAa7 Activate Write Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Random Row Write (Interleaving Banks CLK t CK CKE High CS RAS CAS WE *BS0 A10 ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QAa4 QAa5 QAa6 Write Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Read and Write Cycle ( CLK t CK2 CKE CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ Write Activate Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Read and Write Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 RAa ADD CAa RAa DQM Hi-Z DQ Activate Read Command Command ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Interleaved Column Read Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra ADD DQM AC2 RCD Hi-Z DQ Activate Read Command ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Interleaved Column Read Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 Ra ADD Ca Ra DQM t RCD t RRD Hi-Z DQ Activate Read Command Command ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Interleaved Column Write Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra ADD RCD DQM t RRD Hi-Z DQ DAa0 DAa1 DAa2 DAa3 DBa0 DBa1 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Interleaved Column Write Cycle ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE CS RAS CAS WE *BS0 A10 Ra ADD RCD DQM t RRD Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Auto Precharge after Read Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Auto Precharge after Read Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ Activate Activate Command ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Auto Precharge after Write Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Auto Precharge after Write Burst ( T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 QAa1 QAa2 QAa3 QBa0 QBa1 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Full Page Read Cycle ( CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa Activate Activate Read Command Command Command Bank A Bank B Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Full Page Read Cycle ( CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra ADD Ra Ca DQM Hi-Z DQ Activate Read Command Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR023-0E 6/11/2004 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Full Page Write Cycle ( CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa QAa+1 QAa+2 QAa+3 QAa-1 QAa Write Activate Activate Command Command Command Bank A Bank B Bank A The burst counter wraps ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Full Page Write Cycle ( CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 Ra ADD Ra Ca DQM Hi-Z DQ DAa DAa+1 Write Activate Command Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. DR023-0E 6/11/2004 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Burst Read and Single Write Operation CLK t CK2 High CKE CS RAS CAS WE *BS0 A10 RAa ADD CAa RAa DQM Hi-Z DQ Activate Read Command Command Bank A Bank A BS1=”L”, Bank C,D = Idle 64 Burst Length=4, CAS Latency T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Full Page Random Column Read CLK t CK2 CKE CS RAS CAS WE BS A10 Ra Ra ADD DQM Hi-Z DQ Activate Activate Command Command Command Bank A Bank B Read Command Bank A BS1=”L”, Bank C,D = Idle Integrated Circuit Solution Inc. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Full Page Random Column Write CLK t CK2 CKE CS RAS CAS WE *BS0 A10 Ra Ra ADD DQM Hi-Z DQ QAa0 Activate Activate Command Command Bank A Bank B Write Command Bank A BS1=”L”, Bank C,D = Idle T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Precharge Termination of a Burst ( CLK t CK2 CKE High CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa DQM Hi-Z DQ QAa0 QAa1 QAa2 Activate Write Command Command Bank A Bank A Precharge Termination of a Write Burst. Write data is masked. ...
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... IC42S81600/IC42S81600L IC42S16800/IC42S16800L Precharge Termination of a Burst ( CLK t CK3 CKE High CS RAS CAS WE *BS0 A10 RAa ADD RAa CAa t DPL t DQM RCD Hi-Z DQ DAa0 DAa1 Precharge Activate Write Command Command Command Bank A Bank A Bank A Write Data is masked BS1=”L”, Bank C,D = Idle ...
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... Cycle time (ns) Order Part No. 6 IC42S81600-6TI(G) IC42S81600L-6TI(G) 7.5 IC42S81600-7TI(G) IC42S81600L-7TI(G) 8 IC42S81600-8TI(G) IC42S81600L-8TI(G) 6 IC42S16800-6TI(G) IC42S16800L-6TI(G) 7.5 IC42S16800-7TI(G) IC42S16800L-7TI(G) 8 IC42S16800-8TI(G) IC42S16800L-8TI(G) NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK, Integrated Circuit Solution Inc. DR023-0E 6/11/2004 Package 400mil TSOP-2(Pb-free) 400mil TSOP-2(Pb-free) 400mil TSOP-2(Pb-free) 400mil TSOP-2(Pb-free) 400mil TSOP-2(Pb-free) ...