DM9008F Davicom Semiconductor Incorporated, DM9008F Datasheet

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General Description The DM9008 Ethernet controller is a highly integrated design that provides all Medial Access Control (MAC) and Encode- Decode (ENDEC) functions in accordance with the IEEE 802.3 standard. Network interfaces include 10BASE5 or 10BASE2 Ethernet via the AUI ...

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Features Single chip solution for IEEE T 10BASE2 and 10BASE5 Integrated ISA interface, 8Kx16 SRAM, Media Access T Control, ENDEC and 10BASE-T transceiver Supports ISA Plug and Play configuration T Software-compatible with NOVELL NE2000 T Supports PnP and Non-PnP Auto-switching ...

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Absolute Maximum Ratings* Supply Voltage (VCC -0.5V to +7.0V DC Input Voltage (Vin ...

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DC Electrical Characteristics (continued) Symbol Parameter VDS Differential Squelch Threshold (RX and CD ) VCM Differential Input Common Mode Voltage (RX and CD ) (Note 5) Twisted Pair Interface Pins (TPTX+/TPTX-) Vtidf TP input voltage LI: Vil low Vih high ...

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Pin Description Pin No. Symbol PC ISA BUS INTERFACE PINS SA0 - SA3 SA4 - SA6 7 SA7 9 SA8 SA9 - SA11 SA14 - SA17 20, 22 ...

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IRQ3 8 IRQ4 10 IRQ5 34 IRQ9 IRQ10-12 91 IRQ15 MEMORY INTERFACE PINS 79 EECS 80 BPCS MD0 - MD7 (64) (EEDI) (65) (EEDO) (66) (EECK) (66) (LEDSW) (69) (BNCSW) (70) (SLOT) 63 ...

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Pin Description (continued) Pin No. Symbol NETWORK INTERFACE PINS 39 RX- 40 RX+ 41 CD- 42 CD+ 50 TPTX+ 49 TPTX- 46 TPRX+ 45 TPRX- 5 LILED 76 NC POWER SUPPLY PINS 36, 47, 48 AVCC 43, 44, 51 AGND ...

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ENC Register Address Assignments Page 0 (PS1 = 0, PS0 = 0) SA0-SA3 RD 00H Command (CR) 01H Current Local DMA Address 0 (CLDA0) 02H Current Local DMA Address 1 (CLDA1) 03H Boundary Pointer (BNRY) 04H Transmit Status Register (TSR) ...

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Register Address Assignments (continued) Page 2 (PS1 = 1, PS0 = 0) SA0-SA3 RD 00H Command (CR) 01H ³ Page Start Register (PSTART) 02H Page Stop Register (PSTOP) 03H Remote Next Packet Pointer 04H Transmit Page Start Address 05H Local ...

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Register Descriptions Configuration Register A (CRA) Configuration Register A can be read at address 0AH in Page 0 of ENC, and can be written by following a read to address 0AH with a write to address 0AH. If address 0AH ...

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Configuration Register B (CRB) Configuration Register B can be read at address 0BH in Page 0 of ENC, and can be written by following a read to address 0BH with a write to address 0BH write to address ...

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Configuration Register C (CONFIG.C) This register is configured during RESET and EEPROM read states. CONFIG.C can be read from address 0BH of page 2 of ENC PnP Bit Symbol BPS0 BOOT PROM Select: Selects ...

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Configuration Register D (CONFIG. D) This register can be read or written at register 07H of ENC Page 3. All bits of this register are power-on low EEMODE -- Bit Symbol 0 EEDI EEPROM DATA IN: This bit ...

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Interrupt Line Status Register The logic value of DM9008's eight interrupt pins can be read in register 09H of ENC, page IRQ15 IRQ12 Bit Symbol IRQ3-15 INTERRUPT LINE STATUS: The logic values of interrupt ...

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Command Register (CR) The Command Register is used to initiate transmissions, enable or disable Remote DMA operations, and select register pages. To issue a command, the microprocessor sets the corresponding bit(s) (RD2, RD1, RD0, TXP). Further commands may be overlapped, ...

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Data Configure Register (DCR) This register is used to program the DM9008 for the 8 or 16-bit memory interface, select byte ordering in 16-bit applications, and establish FIFO thresholds. The DCR must be initialized prior to loading the Remote Byte ...

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Transmit Configuration Register (TCR) The transmit configuration register determines the actions of the transmitter section of the DM9008 during transmission of a packet on the network. LB1 and LB0 power Bit Symbol D0 ...

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Transmit Status Register (TSR) This register records events that occur on the media during transmission of a packet cleared when the next transmission is initiated by the host. All bits remain low unless the event that corresponds to ...

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Receive Configuration Register (RCR) This register determines the operation of the NIC during reception of a packet, and is used to program what types of packets to accept Bit Symbol D0 SEP Save Errored Packets 0: ...

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Receive Status Register (RSR) This register records the status of the received packet, including information on errors and the type of address match, either physical or multicast. The contents of this register are written to buffer memory by the DMA ...

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Interrupt Mask Register (IMR) The Interrupt Mask Register is used to mask interrupts. Each interrupt mask bit corresponds to a bit in the Interrupt Status Register (ISR interrupt mask bit is set, an interrupt will ...

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Interrupt Status Register (ISR) This register is accessed to determine the cause of an interrupt. Any interrupt can be masked in the interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing the corresponding bit of ...

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Network Tally Counter Registers (CNTR) Three 8-bit counters are provided for monitoring the number of CRC errors, Frame Alignment Errors and Missed Packets. The maximum count reached by any counter is 192 (C0H). These registers will be cleared when read ...

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MAR0 FB7 FB6 FB5 FB4 MAR1 FB15 FB14 FB13 FB12 MAR2 FB23 FB22 FB21 FB20 MAR3 FB31 FB30 FB29 FB28 MAR4 FB39 FB38 FB37 FB36 MAR5 FB47 FB46 FB45 FB44 MAR6 FB55 FB54 FB53 FB52 MAR7 ...

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Current Page Register (CURR) This register is used internally by the Buffer Management Logic as a backup register for reception. CURR contains the address of the first buffer to be used for a packet reception, and is used to restore ...

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Functional Description Plug and Play (PnP) Module Auto-configuration Ports Three 8-bit I/O ports are defined for the PnP read/write operations. They are called "Auto-configuration ports", and are listed below. Port Name Type ADDRESS W WRITE DATA W READ DATA R ...

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Card Control Registers Index Name 00H Set RD_DATA port 01H Serial Isolation 02H Config Control 03H Wake[CSN] 04H Resource Data 05H Status 06H Card Select Numbe (CSN) 07H Logical Device Final Version: DM9008-DS-F02 November 30, 2000 ISA/Plug & Play Super ...

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Logical Device Control Registers Index Name 30H Activate 31H I/O Range Check Logical Device Configuration Registers Memory Configuration Registers Index Name 40H BROM base address bits[23:16] 41H BROM base address bits[15:0] 42H Memory Control I/O Configuration Registers Index Name 60H ...

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Interrupt Configuration Registers Index Name 70H IRQ level 71H IRQ type bits[7:0] DMA Configuration Registers Index Name 74H DMA channel select 0 75H DMA channel select 1 Vendor Defined Registers Index Name F0H CONFIG A F1H CONFIG B F2H CONFIG ...

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Initial Values of CONFIG.A-D after PC Hardware Reset CONFIG A Bit 7 Mode FREAD DM Jumperless 9346 Plug and Play CONFIG B Bit 7 Mode -- DM Jumperless 0 Plug and Play CONFIG C Bit 7 Mode -- DM Jumperless ...

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Isolation Protocol A simple algorithm is used to isolate each Plug and Play card. This algorithm uses the signals on the ISA bus. It requires lock-step operation between the Plug and Play hardware and the isolation software. Figure 1. Plug ...

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Serial Identifier The key element of the Plug and Play isolation protocol is that each card contains a unique number called a serial identifier. The serial identifier is a 72-bit unique, non-zero number composed of two 32-bit fields and 8-bit ...

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Software Protocol The Plug and Play software sends the initiation Key to all Plug and Play cards to place them into configuration mode. The software is then ready to perform the isolation protocol. The Plug and Play software generates 72 ...

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Reading Resource Data Each PnP card supports a resource data structure stored in a non-volatile device (e.g. 9346) that describes the resources requested by the card. The Plug and Play resource management software will arbitrate resources and set up the ...

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Contents of EEPROM (93C46) in DM9008 Word 00H 01H 02H 03H 06H 07H 08H 09H 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 3FH PS: *1. Operation mode to meet the different reqirement, DM9008 offers three operation mode: 1. ...

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ENA Module Oscillator The oscillator is controlled Mhz parallel resonant crystal connected between X1 and X2. The 20 MHz output of the oscillator is divided generate the 10 MHz transmit clock for the ENC. ...

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ENC Module Transmit Parallel/Serial At the beginning of each transmission, the preamble and synch generators append 62 bits preamble and 1, 1 synch pattern. The parallel data from the FIFO are then serialized for transmission. The serial ...

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Remote DMA The Remote DMA channel is used both to assemble packets for transmission and to remove received packets from the Receive Buffer Ring. It may also be used as a general purpose slave DMA channel for moving blocks of ...

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Preamble and Start of Frame Delimiter (SFD) The Manchester encoded alternating 1, 0 preamble field is used by the ENA to acquire bit synchronization with an incoming packet. When transmitted, each packet contains 62 bits of alternating 1, 0 preamble. ...

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Packet Reception The local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256-byte (128-word) buffers for storage of received packets. The location of the Receive Buffer Ring is programmed in two registers: ...

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Buffer Ring Overflow If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the incoming packet will be aborted by the ENC. Thus, the packets previously received and still contained in the Ring ...

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Removing Packets from the Ring Packets are removed from the ring using either the Remote DMA or an external device. When the Remote DMA is used, the Send Packet command can be used. This programs the Remote DMA to automatically ...

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Prior to transmission, TPSR and TBCR0, TBCR1 must be initialized. To initiate transmission of the packet, the TXP bit in the Command Register is set. The Transmit Status Register (TSR) is cleared and DM9008 begins to transmit data from memory ...

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Restrictions During Loopback The FIFO is split into two halves. The first half is used for transmission, the second for reception. Because only 8-bit fields can be fetched from memory, two tests are required for 16-bit systems to verify the ...

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Alignment of the Received Packet in the FIFO Reception of the packet in the FIFO begins at location zero. After the FIFO pointer reaches the last location in the FIFO, the pointer wraps to the top of the FIFO, overwriting ...

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Remote Read Timing 1) The DMA reads a byte/word from local buffer memory and writes the byte/word into the latch, increments the DMA address, and decrements (RBCR0, 1 the byte from local buffer memory is not available, IOCHRDY ...

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Functional Description TPMAU Function TPMAU receives transmit data and transfers the data to the TP network. The input must be transformer-coupled to the AUI circuit. The receiver is able to pass differential signals as small as 300 mV peak and ...

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Link Integrity Function In the absence of receive traffic, the twisted-pair receiver on the chip can detect periodic link-integrity pulses. A link-integrity pulse is a 100ns high signal with pre-distortion followed by a return to idle. The chip provides a ...

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Timing Specifications: Register Read Timing Symbol t System Address Valid to IOR Low SARL t IOR Low to IOCHRDY Low RLIL t IOCHRDY Width IW t IOCHRDY High to System Data Valid IHSDV t IOR High to System Data Tristate ...

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Register Write Timing Symbol t System Address Valid to IOW Low SAWL t IOW Low to IOCHRDY Low WLIL t IOCHRDY Width IW t System Data Setup SDS t System Data Hold SDH t IOW High to System Address Invalid ...

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SA0 SA16L IO16 SD0-15 t WLIL ZA1-13 (INTERNAL (INTERNAL) ZD0-15 (INTERNAL) Final Version: DM9008-DS-F02 November 30, 2000 Internal Remote DMA Buffer Memory Read Timing ...

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Internal Remote DMA Memory Read Timing Symbol t System Address Valid to IO16 Low SA16L t IOR High to System Data Tristate RDZ t IOCHRDY High to System Data Valid IHSDR t IOR Low to IOCHRDY Low (Note 1) RLIL ...

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Internal Remote DMA Memory Write Timing Symbol t System Address Valid to IO16 Low SA16L t System Data Setup SDS t System Data Hold SDH t IOW Low to IOCHRDY Low (Note 1) WLIL t IOCHRDY High to WERAM Low ...

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Boot-ROM Read Timing Symbol t SMEMR Low to BPCS Low MLOL t SMEMR High to BPCS High MHOH t SMEMR High to System Data Tristate MHDZ t Boot-ROM Data to System Data Valid BDSD t BPCS Low to Boot-ROM Data ...

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Reset Timing Symbol t Software Reset Pulse Width SRSTW tH Hardware Reset Pulse Width RSTW Final Version: DM9008-DS-F02 November 30, 2000 Reset Timing Parameter ISA/Plug & Play Super Ethernet Contoller Min. Max. 1500 205 DM9008 Unit ...

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AC Characteristics Oscillator Specifications Symbol Transmit Clock High XTH Transmit Clock Low XTL Transmit Specifications (Start of Packet) Symbol t Transmit Output Rise Time (20% to 80%) TOr t Transmit Output Fall Time (80% ...

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AC Characteristics Symbol Receive Timing t TPRX+ high to idle time ROFF Link Integrity Timing t Transmitted link integrity pulse period LP t Link integrity pulse width for TPTX LPWD Final Version: DM9008-DS-F02 November 30, 2000 Parameter Receive Timing Transmitted ...

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AC Timing Test Conditions All specifications are valid only if mandatory isolation is employed and all differential signals are taken the AUI side of the pulse tranformer. Input pulse level . . . . . . . ...

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Package Information QFP 100L Outline Dimensions 100 See Detail F Seating Plane Notes: 1. Dimensions D&E do not include resin fins. 2. Dimensions G design reference only. Final Version: DM9008-DS-F02 November 30, ...

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APPENDIX A 1. Application Circuit (for reference only) 60 ISA/Plug & Play Super Ethernet Contoller Version: DM9008-DS-F02 DM9008 Final November 30, 2000 ...

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Oscillator The oscillator is controlled Mhz parallel resonant crystal connected between X1 and external clock on X2. The 20 Mhz output of the oscillator is divided generate the 10 ...

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PC Board Layout Considerations The DM9008 pinout configuration is arranged in accordance with the pin configuration of the ISA-Bus. At the same time, the PC board optimizes layout trace with the larger ground. Analog Trace Routing The cardinal rule ...

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APPENDIX B Plug and Play Function Descriptions DM9008 Configuration Modes DM9008 is power-on in jumperless mode. DM9008's resource configuration information, such as I/O base address, BROM memory base address, interrupt request line, etc., are stored in the CONFIGA-D registers, as ...

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Plug and Play Isolation Sequence The Plug and Play isolation sequence is divided into four states: Wait for Key, Sleep, Isolation, and Config states. The state transitions for the Plug and Play ISA card are shown below: Notes: 1. CSN ...

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Contents of EEPROM (93C46) in DM9008 Word PS: *1. Operation mode to meet the different reqirement, DM9008 offers three operation mode: 1. Auto-Detection (default): any value except 0X4A and 0X50. 2. Jumpless mode: 0X4A ("J") 3. PnP mode: 0X50 ("P") ...

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Introduction to the Plug&Play Function of DM9008 The Plug&Play is a mechanism to provide automatic configuration ability to ISA card in the PC. About the Plug&Play Specification, please reference to "Plug and Play ISA Specification" issued by Intel Corporation and ...

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In the DM9008 design, 2 LED applications may be used LED is used, it will meet the link and traffic LED driver link-pass, the pin outputs low for 80ms and then goes into LED Pin ...

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... Ordering Information Part Number Pin Count DM9008F 100 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, implied or by description ...