DM9101F ETC-unknow, DM9101F Datasheet
DM9101F
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DM9101F Summary of contents
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General Description The DM9101 is a physical-layer, single-chip, low-power transceiver for 100Base-TX, and 10Base-T operations. On the media side, it provides a direct interface either to Unshielded Twisted Pair Category 5 Cable (UTP5) for 100Base-TX Fast Ethernet, or UTP5/UTP3 Cable ...
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... Table of Contents General Description ................................................1 Block Diagram ........................................................1 Features .................................................................3 Pin Configuration: DM9101E LQFP.........................3 Pin Configuration: DM9101F QFP...........................4 Pin Description .......................................................5 Functional Description MII Interface ......................................................12 100Base-TX Operation ......................................14 100Base-TX Transmit........................................14 100Base-TX Operation ......................................15 4B5B Encoder ...................................................15 Scrambler..........................................................15 Parallel to Serial Converter ................................15 NRZ to NRZI Encoder........................................15 MLT-3 Converter ...............................................15 MLT-3 Driver .....................................................15 4B5B Code Group .............................................16 100Base-TX Receiver ...
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Features 10/100Base-TX physical-layer, single-chip transceiver Compliant with IEEE 802.3u 100Base-TX standard Compliant with ANSI X3T12 TP-PMD 1995 standard Compliant with IEEE 802.3u Auto-negotiation protocol for automatic link type selection Supports the MII with serial management interface Supports Full Duplex operation ...
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... Pin Configuration: DM9101F QFP RXI- 9 RXI 10TXO- 10TXO ...
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Pin Description Pin No. Pin Name LQFP QFP MII Interface 54 56 TX_ER/ TXD4 55- TXD3 TXD2 TXD1 TXD0 61 63 TX_EN 62 64 TX_CLK 63 65 MDC 64 66 MDIO 67- RXD3 RXD2 ...
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Pin Description (continued) Pin No. Pin Name LQFP QFP MII Interface (continued CRS 75 77 COL 76 78 RX_DV 77 79 RX_ER/ RXD4 78 80 RX_EN Media Interface RXI-, RXI+ 11, 12 13, 14 ...
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Pin Description (continued) Pin No. Pin Name LQFP QFP LED Interface : These outputs can directly drive LEDs or provide status information to a network management device FDXLED# (POLLED COLLED LINKLED# (TRAFFIC LED) 52 ...
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Pin Description (continued) Pin No. Pin Name LQFP QFP Device Configuration/Control/Status Interface (continued) 88- OPMODE0 OPMODE1 OPMODE2 OPMODE3 92 94 RTPR/NOD BPALIGN 8 10/100Mbps Ethernet Physical Layer Single Chip Transceiver I/O OPMODE0 - OPMODE3: ...
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Pin Description (continued) Pin No. Pin Name LQFP QFP Device Configuration/Control/Status Interface (continued BP4B5B 95 97 BPSCR 96 98 10BTSER Clock Interface 27 29 OSCI/ OSC/XTL CLK25M Final Version: DM9101-DS-F03 July ...
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Pin Description (continued) Pin No. Pin Name LQFP QFP PHY Address Interface: PHYAD[4:0] provides unique PHY address. An address selection of all zeros (00000) will result in a PHY isolation condition. See the isolate bit description in ...
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Pin Description (continued) Power and Ground Pins : The power (VCC) and ground (GND) pins of the DM9101 are grouped in pairs of two categories - Digital Circuitry Power/Ground Pairs and Analog Circuitry Power/Ground Pair. Pin No. Pin Name LQFP ...
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Functional Description The DM9101 Fast Ethernet single-chip transceiver, provides the functionality as specified in IEEE 802.3u, integrates a complete 100Base-TX module and a complete 10Base-T module. The DM9101 provides a Media Independent Interface (MII) as defined in the IEEE 802.3u ...
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MII Interface (continued) TX_ER (transmit coding error) transitions synchronously with respect to TX_CLK. If TX_ER is asserted for one or more clock periods, and TX_EN is asserted, the PHY will emit one or more symbols that are not part of ...
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Operation The 100Base-TX transmitter receives 4-bit nibble data clocked in at 25MHz at the MII, and outputs a scrambled 5-bit encoded MLT-3 signal to the media at 100Mbps. The on-chip clock circuit converts the 25MHz clock into a 125MHz ...
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Operation The block diagram in figure 3 provides an overview of the functional blocks contained in the transmit section. The transmitter section contains the following functional blocks: - 4B5B Encoder - Scrambler - Parallel to Serial Converter - NRZ ...
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Code Group Symbol 10/100Mbps Ethernet Physical ...
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Binary In 100Base-TX Receiver The 100Base-TX receiver contains several function blocks that convert the scrambled 125Mb/s serial data to synchronous 4-bit nibble data that is then provided to the MII. The receive section contains the following functional blocks: - Signal ...
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Clock Recovery Module The Clock Recovery Module accepts NRZI data from the MLT-3 to NRZI decoder. The Clock Recovery Module locks onto the data stream and extracts the 125Mhz reference clock. The extracted and synchronized clock and data are presented ...
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Auto-Negotiation (continued) Auto-negotiation also provides a parallel detection function for devices that do not support the Auto- negotiation feature. During Parallel detection there is no exchange of configuration information, instead, the receive signal is examined discovered that ...
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Register Description Register Address Register Name 0 BMCR 1 BMSR 2 PHYIDR1 3 PHYIDR2 4 ANAR 5 ANLPAR 6 ANER 16 DSCR 17 DSCSR 18 10BTCSR Others Reserved Key to Default In the register description that follows, the default column ...
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Basic Mode Control Register (BMCR) - Register 0 Bit Bit Name 0.15 Reset 0.14 Loopback 0.13 Speed Selection 0.12 Auto-negotiation Enable 0.11 Power Down 0.10 Isolate Final Version: DM9101-DS-F03 July 22, 1999 10/100Mbps Ethernet Physical Layer Single Chip Transceiver Default ...
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Basic Mode Control Register (BMCR) - Register 0 (continued) Bit Bit Name 0.9 Restart Auto- negotiation 0.8 Duplex Mode 0.7 Collision Test 0.6 Reserved Basic Mode Status Register (BMSR) - Register 1 Bit Bit Name 1.15 100Base-T4 1.14 100Base-TX Full ...
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Basic Mode Status Register (BMSR) - Register 1 (continued) Bit Bit Name Default 1.6 MF Preamble 0,RO Suppression 1.5 Auto-negotiation 0,RO Complete 1.4 Remote Fault 0, RO/LH 1.3 Auto-negotiation 1,RO/P Ability 1.2 Link Status 0,RO/LL 1.1 Jabber Detect 0, RO/LH ...
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PHY Identifier Register #2 (PHYIDR2) - Register 3 Bit Bit Name 3.15-3.10 OUI_LSB <101110>,RO/P 3.9-3.4 VNDR_MDL <000000>,RO/P 3.3-3.0 MDL_REV <0010>,RO/P Auto-negotiation Advertisement Register (ANAR) - Register 4 This register contains the advertised abilities of the DM9101 device as they will ...
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Auto-negotiation Advertisement Register (ANAR) - Register 4 (continued) Bit Bit Name 4.6 10_FDX 4.5 10_HDX 4.4-4.0 Selector <00001>, RW Auto-negotiation Link Partner Ability Register (ANLPAR) - Register 5 This register contains the advertised abilities of the link partner as they ...
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Auto-negotiation Expansion Register (ANER) - Register 6 Bit Bit Name 6.15-6.5 Reserved 6.4 PDF 6.3 LP_NP_ABLE 6.2 NP_ABLE 6.1 PAGE_RX 6.0 LP_AN_ABLE DAVICOM Specified Configuration Register (DSCR) - Register 16 Bit Bit Name 16.15 BP_4B5B 16.14 BP_SCR 16.13 BP_ALIGN 16.12 ...
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DAVICOM Specified Configuration Register (DSCR) - Register 16 (continued) Bit Bit Name 16.11 REPEATER 16.10 TX 16.9 UTP 16.8 CLK25MDIS 16.7 F_LINK_100 16.6 Reserved 16.5 LINKLED_CTL 16.4 FDXLED_MODE 16.3 SMRST 16.2 MFPSC Final Version: DM9101-DS-F03 July 22, 1999 10/100Mbps Ethernet ...
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DAVICOM Specified Configuration Register (DSCR) - Register 16 (continued) Bit Bit Name 16.1 SLEEP 16.0 RLOUT DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 Bit Bit Name 17.15 100FDX 17.14 100HDX 17.13 10FDX 17.12 10HDX 17.11- Reserved 17.10 ...
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DAVICOM Specified Configuration and Status Register (DSCSR) - Register 17 (continued) Bit Bit Name 17.3-17.0 ANMB[3:0] 10Base-T Configuration/Status (10BTCSRCSR) - Register 18 Bit Bit Name 18.15 Reserved 18.14 LP_EN 18.13 HBE Pin94),RW 18.12 Reserved 18.11 JABEN 18.10 10BT_SER 18.9-18.1 Reserved ...
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Configuration/Status (10BTCSRCSR) - Register 18 (continued) Bit Bit Name 18.0 POLR Absolute Maximum Ratings* Operating Voltage (VCC) 4.75V to 5.25V Non-Operating Voltage (VCC) -0.5V to 7.00V DC Input Voltage (VIN) -0.5V to VCC +0.5V DC Output Voltage (VOUT) -0.5V ...
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DC Electrical Characteristics Symbol Parameter I Supply Current 100Base-TX 100TX active I Supply Current 10Base-TX active 10TTP (Random data, Random IPG and Random size) I Supply Current 10Base-TX active 10TWC (Max. Packet size, Min. IPG and Worst case data patern) ...
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AC Electrical Characteristics Symbol Parameter Transmitter t 100TXO+/- Differential Rise/Fall TR/F Time t 100TXO+/- Differential Rise/Fall TM Time Mismatch t 100TXO+/- Differential Output TDC Duty Cycle Distortion t 100TXO+/- Differential Output T/T Peak-to-Peak Jitter XOST 100TXO+/- Differential Voltage Overshoot MII ...
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MII-100Base-TX Transmit Timing Diagram TXD [0:3 100TX+/- MII-100Base-TX Transmit Timing Parameters Symbol Parameter t TXD[0:3], TX_EN, ...
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MII-100Base-TX Receive Timing Parameter Symbol Parameter t RXD[0:3), RX_DV, RX_ER Setup RX_CLK High t RXD[0:3], RX_DV, RX_ER Hold RX h From RX_CLK High t RXI In To RXD[0:3] Out ( Latency) t CRS Asserted To ...
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MII-10Base-T Nibble Transmit Timing Diagram TX_CLK TXD [0:3], TX_EN, TX_ER CRS 10TX+/- MII-10Base-T Nibble Transmit Timing Parameters Symbol Parameter t TXD[0:3), TX_EN, TX_ER Setup TX_CLK High t TXD[0:3], TX_EN, TX_ER Hold TX h ...
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MII-10Base-T Receive Nibble Timing Parameters Symbol Parameter t RXD[0:3), RX_DV, RX_ER RX s Setup To RX_CLK High t RXD[0:3], RX_DV, RX_ER Hold RX h From RX_CLK High t RXI In To RXD[0:3] Out ( Latency) t CRS Asserted ...
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Jab and Unjab Timing Parameters Symbol Parameter t Maximum Transmit Time 1 t Unjab Time 2 MDIO Timing when OUTPUT by STA MDIO MDIO Timing when OUTPUT by DM9101 MDIO MII Timing Parameters ...
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Magnetics Selection Guide The DM9101 requires a 1:1 ratio for both the receive and the transmit transformers. Refer to Table 2 for transformer requirements. Transformers meeting these requirements are available from a variety of magnetic manufacturers. Designers should test and ...
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... Ferrite, PanasonicEXCCL4532U Oscillator, Crystal, 25Mhz, 50ppm Transistor, NNP, General Purpose, 2N2222 Resistor, 470 , 5% Resistor, 820 , 5% Resistor Resistor, 510 , 5% Resistor, 6.01K , 1% Resistor, 49 Resistor, 1. Resistor Resistor, 10K , 5% DM9101F, PHY/Transceiver, 100pin QFP Magnetics, Pulse Engineering, PE68515 Table 3 Parts List for Example Design DM9101 39 ...
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10/100Mbps Ethernet Physical Layer Single Chip Transceiver ...
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Package Information LQFP 100L Outline Dimensions 100 See Detail F Seating Plane Symbol Notes: 1. Dimension D & not include resin fins. ...
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Package Information QFP 100L Outline Dimensions See Detail F Seating Plane Symbol Note: 1. Dimension D & ...
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... Ordering Information Part Number Pin Count DM9101E 100 DM9101F 100 Disclaimer The information appearing in this publication is believed to be accurate. Integrated circuits sold by DAVICOM Semiconductor are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. DAVICOM makes no warranty, express, statutory, ...