STP2210QFP ETC-unknow, STP2210QFP Datasheet
STP2210QFP
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STP2210QFP Summary of contents
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... High integration • Allows design of low-cost, low-chip-count embedded systems • Ease of design and testability • Low cost Part Number STP 2200ABGA Uniprocessor System Controller STP2210QFP Reset/Interrupt/Clock Controller STP2220ABGA UPA to SBus I/O interface controller STP2222ABGA UPA to PCI bus I/O Interface controller STP2230SOP Crossbar Data Path ...
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USC STP2200ABGA Uniprocessor System Controller LOCK AND YPICAL PPLICATION UPA_ADDRBUS0[34:0] UPA_ADR0_PAR0 UPA_ADDR0_VAL0[1:0] UPA_SC_REQ0 UPA_REQIN0[1:0] Port Interface UPA_ADDRBUS1[28:0] UPA_ADDR1_VAL1 UPA_PREPLY0[4:0] UPA_PREPLY1[4:0] UPA_PREPLY2[4:0] SYS_RESET X_BUTTON_RESET P_BUTTON_RESET UPA_RESET0 UPA_RESET1 UPA_XIR EBus Interface EBUS_CS EBUS_RD EBUS_WR EBUS_RDY EBUS_ADDR[2:0] EBUS_DATA[7:0] CLK + ...
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STP2200ABGA Uniprocessor System Controller (USC) Figure 2. USC Typical Application Diagram July 1997 Uniprocessor System Controller UPA_ADDRBUS1 UPA_64S STP2220ABGA UPA-to-SBus Interface (U2S) UPA_ADDRBUS0 or STP2xxxABGA UPA-to-PCI Interface (U2P) CPU 144 Processor Data Bus BMX_CMD0[3:0] BMX_CMD1[3:0] STP2230SOP MRB_CTRL Crossbar Switch Array ...
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USC STP2200ABGA Uniprocessor System Controller S D IGNAL ESCRIPTIONS UPA Interface Signals Signal I/O UPA_ADDRBUS0[34:0] I/O Address bus 0 (processor/U2S) UPA_ADR0_PAR I/O Parity for address bus 0 UPA_ADDR0_VAL[1:0] I/O [0] = processor, [1] = U2S UPA_SC_REQ0 O USC request for ...
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Crossbar Interface Signals Signal Type BMX_CMD1[3:0] O Duplicate of BMX_CMD0[3:0] MRB_CTRL1 O Duplicate of MRB_CTRL0 MWB_CTRL1 O Duplicate of MWB_CTRL0 EBus Signals Signal Type Condition EBUS_DATA[7:0] I/O 5-V tolerant EBUS_CS I 5-V tolerant EBUS_ADDR[2:0] I 5-V tolerant EBUS_RDY O EBUS_WR ...
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USC STP2200ABGA Uniprocessor System Controller Power and Ground Signal PLL_VDD Power for PLL PLL_GND Ground for PLL V 5-V reference for 5-V tolerant inputs CC 6 Description July 1997 ...
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T O ECHNICAL VERVIEW The USC implements three UPA ports on two address buses. It has a programmable memory controller and an EBus interface. Addresses flow through the USC. Data flows through the crossbar switches. UPA Port Interface (PIF) The ...
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USC STP2200ABGA Uniprocessor System Controller • MC_Control 0; and • MC_Control 1 These registers are described in further detail in the USC User Guide. EBus Interface (EB) The EB implements an interface to EBus, an asynchronous 8-bit interface controlled by ...
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E S LECTRICAL PECIFICATIONS [1] Absolute Maximum Ratings Symbol V DC supply voltage reference voltage CC V Input voltage (any pin Continuous power dissipation D T Storage temperature range STG 1. Operation of the device ...
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USC STP2200ABGA Uniprocessor System Controller = DC Characteristics Symbol Parameter V Input low voltage IL V Input high voltage IH V Input low voltage, CLK + / – Input high voltage, CLK + / – Input ...
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AC C HARACTERISTICS Nearly all inputs and outputs are registered and are referenced to the PECL differential input clock (CLK+ and CLK–). This clock input controls an on-board PLL. These signals are clocked by the rising edge of CLK+ at ...
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USC STP2200ABGA Uniprocessor System Controller AC Characteristics, Signals Referenced to Rising Edge of UPA_CLK Parameter Signal Name t UPA signals SU t UPA signals H t UPA signals UPA signals VO t BMX_CMD0[3: ...
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Signal Timing Definition CLK+ CLK– Input Output Figure 3. Signal Timing Definition PLL Specifications PLL and Clock Distribution Circuitry The schematic below shows the PLL scheme inside the USC. BIED03T FBIN FBOUT CLK+ P CLK– N ...
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USC STP2200ABGA Uniprocessor System Controller T D IMING IAGRAMS Bus Timings All data transfers have a dead cycle between them, except for back-to-back single writes from the processor to a graphics slave device. The following diagrams show some best-case response ...
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Figure 8 and Figure 9 show the best-case timing for non-cacheable single and block read from U2S referenced to the time the P_Reply is issued from the slave. The timing for non-cacheable read from the fast frame buffer (FFB) (UPA64S) ...
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USC STP2200ABGA Uniprocessor System Controller UPA_ADDRBUS0 UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxx DATA_STALL UPA_DATA 64 UPA_DATA 128 Figure 10. Best-Case Timing for Non-Cached Single Write, UPA128 -> UPA64 UPA_ADDRBUS0 ...
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UPA_PREPLY P_RASB UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxx DATA_STALL UPA_DATA 64 UPA_DATA 128 Figure 13. Best-Case Timing for Noncached Block Read, UPA64 -> UPA64 Figure 14 and Figure 15 show the best-case ...
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USC STP2200ABGA Uniprocessor System Controller Figure 16 and Figure 17 show the nominal timing for a U2S non-cacheable single and block read from the processor UPA_PREPLY P_RASB UPA_SREPLY to master UPA_SREPLY to slave BMX_CMD xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxx ...
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UPA_ADDRBUS0 PReq0 MEMADDR[12:0] RAS Figure 18. Best-Case PRequest-to-Memory Request Timing, Read (Fast Path) Figure 19 shows a read or write issued through the “normal path.” PReq0 UPA_ADDRBUS0 MEMADDR[12:0] RAS Figure 19. Best-Case PRequest-to-Memory Request Timing (Normal Path) July 1997 ...
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USC STP2200ABGA Uniprocessor System Controller 20 ...
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RAS CAS Fixed at One Clock 1. RAS is the minimum RAS timing the RAS-precharge timing. UPA-to-Memory Timing Figure 22 and Figure 23 show the minimum time for a UPA memory request packet issued on the UPA ...
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USC STP2200ABGA Uniprocessor System Controller UPA_ADDRBUS0 MEMADDR[12:0] RAS Figure 23. Best-Case UPA-to-Memory Timing (Normal Path) Note: Fast path timing is only applicable for memory reads issued from the processor. All other memory accesses use the normal path. Default Memory Timing ...
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MEMADDR xxxxxxxxxxxx Row xxxxxxxxxxxxxxxxxxxx RAS CAS xxxxxxxxxxxx WE xxxxxxxxxxxx xx MRB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA UPA_DATA_STALL xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Figure 25. Default Memory CPU Write Timing MEMADDR Row xxxx xx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx RAS ...
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USC STP2200ABGA Uniprocessor System Controller MEMADDR xxxxxxxxxxxxxxxx RAS xxxxxxxxxxxxxxxxxxxxxxx CAS xxxxxxxxxxxxxxxx WE xxxxxxxxxxxxxxxx xx MRB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (U2S) MEMDATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx UPA_DATA_STALL Figure 27. Default Memory U2S Write Timing xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx ...
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MHz (12 ns) Timings xxxxx x Row MEMADDR x xxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxx x RAS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx CAS WE xxxxxxxxxxxxxxxxx xxx MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA xxxxxxxxxxxxxxxxxxxxxxxx x x UPA_DATA_STALL Row MEMADDR xxxxxxxxxxx xxxxxxxxxxxxxxxxxxx ...
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USC STP2200ABGA Uniprocessor System Controller Row MEMADDR xxxxx x x xxxxxxxxxxxx x xxxxxxxxxxxxxxxxxxxxxxxxxxx RAS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx CAS WE xxxxxxxxxxxxxxxxx xx MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxx x UPA_DATA_STALL Figure 31. 83.3 MHz U2S Read Timing 0 1 ...
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MEMADDR xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxx xx xx RAS xxxx x xx xxxxxxxxxxxxx CAS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxx MWB_CTRL xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MRB_CTRL xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MEMDATA 71.4 MHz (14 nanoseconds) Timings 0 ...
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USC STP2200ABGA Uniprocessor System Controller MEMADDR xxxxxxxxxxx Row xx xx xxxxxxxxxxxxxxxxxxx xx RAS xxxxxxxxxxx xx xx CAS xxxxxxxxxxx xxx xx MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (CPU) MEMDATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx UPA_DATA_STALL Figure 35. 71.4 ...
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MEMADDR Row xxxxxxxxxxxxxxxx RAS xxxxxxxxxxxxxxxxxxxxxxxx CAS xxxxxxxxxxxxxxxx WE xxxxxxxxxxxxxxxx xx MWB_CTRL UPA_SREPLY BMX_CMD UPA_DATA (U2S) MEMDATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx UPA_DATA_STALL xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx x MEMADDR x x xxxx x xxxxxxxxxxxxx RAS x x ...
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USC STP2200ABGA Uniprocessor System Controller Minimum Timings Figure 39 through Figure 43 show the absolute minimum timing that the memory controller is capable of generating MEMADDR Row Column 0 xxxx xx xx RAS xxxxxxxxx xx xxxxxxxxxxxxxxxxx ...
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MEMADDR xxxx xx xx Row Column 0 xxxxxxxxx xx xxxxxxxxxxxxxxxxx xx RAS xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xx CAS xxxxxxxxx xx xx MRB_CTRL UPA_SREPLY BMX_CMD MEMDATA UPA_DATA xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx UPA_DATA_STALL MEMADDR xxxxxxxxxxxxxxxxxxx RAS ...
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USC STP2200ABGA Uniprocessor System Controller xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx MEMADDR xxxxxxx x x RAS xxxx xx xxxxxxxxxxx CAS xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxx MWB_CTRL xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MRB_CTRL xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx MEMDATA 32 5 ...
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EBus Timing Figure 44 and Figure 45 show external timing for EBus accesses. EBUS_CS EBUS_ADDR[2:0] EBUS_RD EBUS_WR EBUS_RDY EBUS_DATA[7:0] Figure 44. External EBus Read Timing EBUS_CS EBUS_ADDR[2:0] EBUS_WR EBUS_RD EBUS_DATA[7:0] EBUS_RDY Figure 45. External EBus Write Timing July 1997 USC ...
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USC STP2200ABGA Uniprocessor System Controller P I ACKAGE NFORMATION 225-Pin Plastic Ball Grid Array (ABGA) Pin Assignments Pin Signal Name Pin Signal Name UPA_PREPLY1_1 D2 BMX_CMD0_2 A3 JTAG_TRST D3 UPA_SREPLY0_0 ...
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Plastic ABGA Package Dimensions 27.00 ± 0.10 Square 24.00 ± 0.10 Square Position A1 Indicator 0.78 DIA Approx. (Gold plated) Notes: 1. Drawing is not to scale. 2. Unless otherwise specified, all dimensions are in millimeters. Nonlimited dimensions other ...