A29040AL-70 AMIC Technology Corporation, A29040AL-70 Datasheet

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A29040AL-70

Manufacturer Part Number
A29040AL-70
Description
Manufacturer
AMIC Technology Corporation
Datasheet

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The A29040A is a 5.0 volt-only Flash memory organized as
524,288 bytes of 8 bits each. The 512 Kbytes of data are
further divided into eight sectors of 64 Kbytes each for flexible
sector erase capability. The 8 bits of data appear on I/O
while the addresses are input on A0 to A18. The A29040A is
offered in 32-pin PLCC, TSOP, and PDIP packages. This
device is designed to be programmed in-system with the
standard system 5.0 volt VCC supply. Additional 12.0 volt VPP
is not required for in-system write or erase operations.
However, the A29040A can also be programmed in standard
EPROM programmers.
The A29040A has a second toggle bit, I/O
whether the addressed sector is being selected for erase, and
also offers the ability to program in the Erase Suspend mode.
The standard A29040A offers access times of 55, 70 and 90
ns, allowing high-speed microprocessors to operate without
wait states. To eliminate bus contention the device has
separate chip enable (
enable (
The device requires only a single 5.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Preliminary
Features
n 5.0V
n Access times:
n Current:
n Flexible sector architecture
n Embedded Erase Algorithms
General Description
PRELIMINARY
- 8 uniform sectors of 64 Kbyte each
- Any combination of sectors can be erased
- Supports full chip erase
- Sector protection:
- 55/70/90 (max.)
- 20 mA typical active read current
- 30 mA typical program/erase current
- 1 A typical CMOS standby
- Embedded Erase algorithm will automatically erase
A hardware method of protecting sectors to prevent
any inadvertent program or erase operations within
that sector
the entire chip or any combination of designated
sectors and verify the erased sectors
OE
10% for read and write operations
) controls.
(August, 2001, Version 0.1)
CE
), write enable ( WE ) and output
2
, to indicate
0
- I/O
7
1
n Typical 100,000 program/erase cycles per sector
n 20-year data retention at 125 C
n Compatible with JEDEC-standards
n
n Erase Suspend/Erase Resume
n Package options
The A29040A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin.
512K X 8 Bit CMOS 5.0 Volt-only,
- Embedded Program algorithm automatically writes
- Reliable operation for the life of the system
- Pinout and software compatible with single-power-
- Superior inadvertent write protection
- Provides a software method of detecting completion
- Suspends a sector erase operation to read data from,
- 32-pin P-DIP, PLCC, or TSOP (Forward type)
Data
Uniform Sector Flash Memory
and verifies bytes at specified addresses
supply Flash memory standard
of program or erase operations
or program data to, a non-erasing sector, then
resumes the erase operation
Polling and toggle bits
-
an
internal
A29040A Series
AMIC Technology, Inc.
algorithm
that
automatically

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A29040AL-70 Summary of contents

Page 1

Preliminary Features n 5.0V 10% for read and write operations n Access times: - 55/70/90 (max.) n Current typical active read current - 30 mA typical program/erase current - 1 A typical CMOS standby n Flexible sector ...

Page 2

... Power consumption is greatly reduced when the device is placed in the standby mode. n PLCC VCC A17 30 A14 A13 A11 25 A29040AL A10 I I I/O ...

Page 3

Block Diagram VCC VSS State WE Control Command Register CE OE VCC Detector A0-A18 Pin Descriptions PRELIMINARY (August, 2001, Version 0.1) Erase Voltage Generator PGM Voltage Generator Chip Enable Output Enable STB Timer Pin No A18 Address Inputs ...

Page 4

Absolute Maximum Ratings* Ambient Operating Temperature . . . . . - 125 C Storage Temperature . . . . . . . . . . . . . . - 125 C VCC ...

Page 5

Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE and OE pins the power control and IL selects the device the output control and ...

Page 6

Autoselect Mode The autoselect mode provides manufacturer and device identification, and sector protection verification, through identifier codes output on I intended for programming equipment to automatically match a device to be programmed with its corresponding programming ...

Page 7

Command Definitions Writing specific address and data commands or sequences into the command register initiates device operations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence ...

Page 8

START Write Program Command Sequence Data Poll from System Embedded Program algorithm in progress Verify Data ? Increment Address Last Address ? Programming Completed Note : See the appropriate Command Definitions table for program command sequence. Figure 1. Program Operation ...

Page 9

Figure 2 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations tables in the "AC Characteristics" section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Erase Suspend/Erase Resume Commands The Erase Suspend ...

Page 10

Command Sequence (Note 1) Read (Note 5) Reset (Note 6) Manufacturer ID Device ID Autoselect Continuation ID (Note 7) Sector Protect Verify (Note 8) Program Chip Erase Sector Erase Erase Suspend (Note 9) Erase Resume (Note 10) Legend ...

Page 11

Write Operation Status Several bits, I/O , I/O , I/O , I/O , and I A29040A to determine the status of a write operation. Table 5 and the following subsections describe the functions of these status ...

Page 12

I/O : Toggle Bit I 6 Toggle Bit I on I/O indicates whether an Embedded Program 6 or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be ...

Page 13

I/O : Sector Erase Timer 3 After writing a sector erase command sequence, the system may read I/O to determine whether or not an 3 erase operation has begun. (The sector erase timer does not apply to the chip erase ...

Page 14

Operation Standard Embedded Program Algorithm Mode Embedded Erase Algorithm Erase Reading within Erase Suspend Suspended Sector Mode Reading within Non-Erase Suspend Sector Erase-Suspend-Program Notes: 1. I/O and I/O require a valid address when reading status information. Refer to the appropriate ...

Page 15

Maximum Negative Input Overshoot +0.8V -0.5V -2.0V Maximum Positive Input Overshoot VCC+2.0V VCC+0.5V 2.0V PRELIMINARY (August, 2001, Version 0.1) 20ns 20ns 20ns 20ns 20ns 20ns 15 A29040A Series AMIC Technology, Inc. ...

Page 16

DC Characteristics TTL/NMOS Compatible Parameter Parameter Description Symbol I Input Load Current Input Load Current LIT I Output Leakage Current LO I VCC Active Read Current CC1 (Notes 1, 2) VCC Active Write (Program/Erase) I CC2 Current ...

Page 17

AC Characteristics Read Only Operations Parameter Symbols JEDEC Std t t Read Cycle Time (Note 2) AVAV RC Address to Output Delay t t AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to ...

Page 18

AC Characteristics Erase and Program Operations Parameter Symbols JEDEC Std t t Write Cycle Time (Note 1) AVAV WC Address Setup Time t t AVWL AS Address Hold Time t t WLAX Data Setup Time DVWH DS ...

Page 19

Timing Waveforms for Program Operation Program Command Sequence (last two cycles Addresses 555h CE t GHWL Data t VCS VCC Note : PA = program addrss program data, Dout is the true ...

Page 20

Timing Waveforms for Chip/Sector Erase Operation Erase Command Sequence (last two cycles Addresses 2AAh CE t GHWL Data t VCS VCC Note : SA = Sector Address Valid Address for reading status ...

Page 21

Timing Waveforms for Data Polling (During Embedded Algorithms Addresses VA t ACC OEH WE I/O 7 I Note : VA = Valid Address. Illustation shows first status ...

Page 22

Timing Waveforms for Toggle Bit (During Embedded Algorithms Addresses VA t ACC OEH WE I Note Valid Address; not required for I/O read cycle, and ...

Page 23

Timing Waveforms for I/O vs. I/O 2 Enter Erase Embedded Suspend Erasing WE Erase Erase Suspend I/O 6 I/O 2 I/O and I/O toggle with OE and Note : Both I/O and I/O toggle with OE or ...

Page 24

Timing Waveforms for Alternate CE Controlled Write Operation 555 for program 2AA for erase Addresses GHEL Data for program 55 for erase Note : Program Address, ...

Page 25

Latch-up Characteristics Input Voltage with respect to VSS on all I/O pins VCC Current Includes all pins except VCC. Test conditions: VCC = 5.0V, one pin at time. TSOP Pin Capacitance Parameter Symbol Parameter Description C Input Capacitance IN C ...

Page 26

Test Conditions Test Condition Output Load Output Load Capacitance, C (including jig capacitance) L Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels Device Under Test PRELIMINARY (August, 2001, Version 0.1) ...

Page 27

... Ordering Information Access Time Part No. (ns) A29040A-55 A29040AL-55 55 A29040AV-55 A29040A-70 A29040AL-70 70 A29040AV-70 A29040A-90 A29040AL-90 90 A29040AV-90 PRELIMINARY (August, 2001, Version 0.1) Active Read Program/Erase Current Current Typ. (mA) Typ. (mA A29040A Series Standby Current Package Typ 32Pin DIP 32Pin PLCC 1 32Pin TSOP ...

Page 28

Package Information P-DIP 32L Outline Dimensions 32 1 Symbol Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. PRELIMINARY (August, 2001, Version 0. Base Plane Seating Plane ...

Page 29

Package Information PLCC 32L Outline Dimension Symbol Notes: 1. Dimensions D and E do not include resin fins. 2. Dimensions G design reference only. PRELIMINARY (August, 2001, Version 0. ...

Page 30

Package Information TSOP 32L TYPE 20mm) Outline Dimensions y Symbol H Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash. PRELIMINARY ...

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