MX10FMAXDQC ETC-unknow, MX10FMAXDQC Datasheet
MX10FMAXDQC
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MX10FMAXDQC Summary of contents
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... P3.3 P3 P/N:PM0626 ADVANCED INFORMATION MX10FMAXDQC SINGLE-CHIP 8-BIT MICROCONTROLLER • Code protection • Two priority levels • Power saving Idle and power down modes • external program memory space • external data memory space • Four 8-bit I/O ports • Full-duplex enhanced UART compatible with the stan- ...
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... BLOCK DIAGRAM Vcc Vss B REGISTER PSEN ALE TIMING AND EA CONTROL RST OSC. XTAL2 XTAL1 P/N:PM0626 MX10FMAXDQC P0.0-P0.7 P2.0-P2.7 PORT 0 PORT 2 DRIVERS DRIVERS PORT 0 PORT 2 RAM LATCH LATCH STACK ACC POINTER TMP2 TMP1 ALU T0/T1/T2 SFRs PSW TIMERS PORT 1 LATCH PORT 1 DRIVERS P1.0-P1.7 2 ROM PROGRAM ADDR. ...
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... As inputs, Port 2 pins that are exter- nally pulled low will source current (IIL, on the data sheet) because of the internal pullups. P/N:PM0626 MX10FMAXDQC Port 2 emits the high-order address byte during fetches from external Program Memory and during accesses to external Data Memory that use 16-bit addresses (MOVX @DPTR) ...
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... ALE pin. PSEN : Program Store Enable is the read strobe to ex- ternal Program Memory. When the MX10FMAXDQC is executing code from ex- ternal Program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external Data memory. ...
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... Power Down. Re- set redefines all the SFRs but does not change the on- chip RAM. An external interrupt allows both the SFRs and on-chip RAM to retain their values. P/N:PM0626 MX10FMAXDQC ABSOLUTE MAXIMUM RATING* Ambient Temperature Under Bias Storage Temperature Voltage on Any Other Pin to VSS ...
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... P2.0 ~ P2.5, P3 A13, A14 ~A15 P0 P3.3 CE P2.7 OE ALE WE EA Vpp P3.7, P3.1, P3.0 MS2 ~ MS0 VDD VDD GND GND Notice for speed progamming P/N:PM0626 MX10FMAXDQC 4.5/5/6.25V VDD RST XTAL1 PSEN 4~6MHz EA XTAL2 P3.3 P0[7:0] P2.7 P2.6 ALE P3[5:4],P2[5:0],P[7:0] P3.7,P3.1, P3.0 VSS FUNCTION Input low order address bits Input high order address bits Data Input/Output ...
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... Pgm Lock bit #1 12.5~13V Pgm Lock bit #2 12.5~13V Pgm Lock bit #3 12.5~13V Pgm verify Lock bits 6.25V Erase verify LOCK bits 4.5V Chip Erase 12.5~13V Erase Verify 12.5~13V Normal Read X P/N:PM0626 MX10FMAXDQC VDD P3.3 P2.7 ALE 6.25V 0 1 100us pulses address 6 ...
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... VDD EA ALE A0=0 / A0=1 ADDRESS tAA P3.3 tCE P2.7 tOE VDD P3.7 000 P3.1,P3.0 GND P0.7-P0.0 Read Signature tAA tCE tOE Mim. Max. 120 120 70 unit P/N:PM0626 MX10FMAXDQC XXX tDF Mft ID/Device ID tDF tDF tAA tCE tOE 100 tDF OUT Normal Read REV. 0.1, DEC 17, 1999 ...
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... ERASE AND VERIFY FLOWCHART P/N:PM0626 MX10FMAXDQC START X LOCK2 is set to 1, Program array all zero we can apply 3 program pulses to each byte (0~64KB) & LOCK and LOCK bits without verifying them VCC=6.25V VPP=12.5V Chip erase (0.5 s) VCC=4.5V VPP=4.5V fail Erase-verify LOCK YES VCC=4.5V VPP=12 ...
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... VDD tVPS P2.7 P3.3 tCES ALE P3.7, P3.1,P3.0 tMS tDS tDH Mim Max. unit us us P/N:PM0626 MX10FMAXDQC ADDRESS VPP=12.5~13V if Erase verify array; VPP=4.5V if Erase verify LOCK bits tEV tER tEW 010 011/101 tMS Erase Verify Array or LOCK bits Erase tVPS tMS tCES ...
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... PROGRAM AND PROGRAM VERIFY FLOWCHART Increment Address P/N:PM0626 MX10FMAXDQC START First Address VCC=6.25V VPP=12.5V X=0 YES Program (20~100us) YES Fail Program x=x+1 Verify YES No Last Address YES VCC=5V VPP=5V Normal Fail Read All Pass Pass Device 11 No X=20 Yes Fail Device REV. 0.1, DEC 17, 1999 ...
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... PROGRAM AND PROGRAM VERIFY FLOWCHART ADDRESS tAS P0.7~P0.0 tDS VPP EA VDD tVPS P2.7 P3.3 tCES ALE P3.7, P3.1,P3.0 tMS tAS tDS Mim Max. unit us us P/N:PM0626 MX10FMAXDQC IN tDH tPR tPW 011 tMS Program tDH tVPS tCES OUT tPV 010 Program Verify tMS tPR tPW tPV ...
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... PROGRAM LOCK BITS AND PROGRAM VERIFY LOCK BITS FLOWCHART P/N:PM0626 MX10FMAXDQC START X=0 VCC=6.25V VPP=12.5V Program (100us) YES VCC=6.25V VPP=6.25V Fail Program X=20 x=x+1 Verify YES Apply 10 program pulses Fail Device to the specified LOCK bit Pass Device 13 No Yes REV. 0.1, DEC 17, 1999 ...
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... P2.7 P3.3 tCES ALE P3.7, P3.1,P3.0 tMS tVPS tCES tMS tPR Mim Max. unit P/N:PM0626 MX10FMAXDQC DON'T CARE 6.25V tPR tPW 111/110/100 tMS Program Lock Bit(#1/#2/#3) tPW tPV 20 105 240 P0.3~P0.1= lock[3:1] tPV 101 Lock bit Verify REV. 0.1, DEC 17, 1999 ...
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... ITL Logical Transition Current (Ports 1, 2 and 3) Industrial PRST RST Pulldown Resistor CIO Pin Capacitance ICC Power Supply Current: Active Mode at 40 MHz Idle Mode at 40 MHz(70° C 5.5V) Power Down Mode P/N:PM0626 MX10FMAXDQC Min Max 0 +70 4.5 5.5 3.5 40 Min Typ Max (Note 4) -0.5 ...
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... Figure 6. ICC Test Condition, Active Mode P/N:PM0626 MX10FMAXDQC 10mA 26mA 15mA 71mA VCC ICC VCC VCC P0 EA All other pins disconnected TCLCH = TCHCL = 5ns 16 VCC ICC VCC VCC P0 EA RST MX10FMAXDQC (NC) XTAL2 CLOCK XTAL1 SIGNAL VSS Figure 7. ICC Test Condition Idle Mode REV. 0.1, DEC 17, 1999 ...
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... The following is a list of all the characters and what they stand for. A: Address C: Clock D: Input Data H: Logic level HIGH L: Logic level LOW, or ALE P: PSEN P/N:PM0626 MX10FMAXDQC VCC ICC VCC VCC P0 EA 0.7 VCC 0.2 VCC-0.1 TCHCX ...
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... TIME FROM HIGH TO ALE HIGH TQVWX DATA VALID TO WR TRANSITION TQVWH DATA SET-UP TIME BEFORE WR TWHQX DATA HOLD TIME AFTER WR TRLAZ ADDRESS FLOAT DELAY AFTER RD NOTE: 1. The maximun operating frequency is limited to 40 MHz and the minimum to 3.5 MHz. P/N:PM0626 MX10FMAXDQC 33 MHz MIN ...
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... VCC+0.9 0.2 VCC-0.1 0.45V AC Inputs during testing are driven at VCC-0.5V for a Logic "1" 0.45V for a Logic "0". Timing measurements are made at VIH min for a Logic "1" and VIL max for a Logic "0". P/N:PM0626 MX10FMAXDQC VARIABLE CLOCK MIN 1 ...
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... EXTERNAL PROGRAM MEMORY READ CYCLE ALE PSEN PORT 0 PORT 2 EXTERNAL DATA MEMORY READ CYCLE ALE TLHLL PSEN RD TAVLL TLLAX PORT 0 A0-A7 FROM RI OR DPL TAVWL PORT 2 P/N:PM0626 MX10FMAXDQC TLHLL TLLPL TPLIP TLHIV TAVLL TPLIV TPLAZ TPXIX TLLAX INSTR IN TAVIV A8 - A15 TLLDL TLLWL TRLRH ...
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... PORT 0 A0-A7 FROM RI OR DPL PORT 2 SHIFT REGISTER MODE TIMING WAVEFORMS 1 0 INSTRUCTION ALE CLOCK TQVXH OUTPUT DATA 0 WRITE TO SBUF INPUT DATA VALID CLEAR RI P/N:PM0626 MX10FMAXDQC TLLWL TWLWH TQVWX TLLAX TQVWH DATA OUT TAVWL P2.0-P2.7 OR A8-A15 FROM DPH TXLXL TXHQX TXHDV ...
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