ES1371 ETC-unknow, ES1371 Datasheet
ES1371
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ES1371 Summary of contents
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... Stereo inputs and 3 mono inputs can be mixed into the output stream. Direct I/O space access of the control registers. 100 Pin PQFP or TQFP 2 External I S input No ISA bus pins required Fully Compliant with PC97 Power Management specification ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997 ES1371 Specification ENSONIQ Proprietary Information 1 ...
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ENSONIQ Proprietary Information 2. DESIGN CONCEPT AudioPCI PCI bus master and slave device that is best understood by looking at the device as four interactive subsystems: the PCI interface, DMA control, LEGACY functions, and the CODEC. 2.1. ...
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ENSONIQ Proprietary Information 3. BLOCK DIAGRAM Legacy Chip Select Ext IRQ & IRQ & GPIO GPIO[3:0] XTALi Clock Generation XTALo Joy[7:0] Joystick ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997 PCI Interface Block Host Interface Control Block Sample Rate ...
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ENSONIQ Proprietary Information 4. THE SYSTEM Components 4.1. PCI Interface/LEGACY The PCI subsystem is a bus master interface that performs the memory accesses to keep the Audio cache buffers full and empties the A/D Converter (or I2S input) buffer to ...
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ENSONIQ Proprietary Information 4.8. UART This block includes both the transmitter and receiver for the AudioPCI 97 MIDI interface. The UART controller also implements an eight byte FIFO in the internal memory. This FIFO is then accessed through the HOST ...
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ENSONIQ Proprietary Information 4.11. Internal Memory There are two separate sections of memory in AudioPCI 97. One section is allocated as a cache for the playback and record channels and also as a FIFO for the UART. The other section ...
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ENSONIQ Proprietary Information The internal memory organization for the Sample Rate Converter in AudioPCI 97 is shown below. The memory is accessed through the Sample Rate Converter interface register located at address 10H. Loc(hex) Fifo Ram 128x16 0 PLAY 1 ...
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ENSONIQ Proprietary Information 5. PCI Data Transfers The internal control registers of the AudioPCI 97 Chip and the AC97 CODEC are accessed via 16 Long Words in PCI direct I/O space. These registers are always read as 32 bit longwords ...
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... These command bits are not implemented and always read back as zeros. PCI Bus Master enable bit. This bit controls a device’s ability to act as a PCI Bus Master. The ES1371 can act as a bus master PCI Bus Mastering disabled PCI Bus Mastering enabled. ...
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ENSONIQ Proprietary Information Status Addressable as word Power on reset value x610H Bit(s) R/W Name 15 R PARITY 14 R SERR MASTER-ABORT 12 R TARGET-ABORT 11 R ZERO 10:9 R DEVSEL# 8:5 R ZERO 4 R CAPABILITIES 3:0 ...
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ENSONIQ Proprietary Information Cache Line Size Addressable as Byte Power on reset value 00H Bit(s) R/W Name 7:0 R CACHE LINE SIZE Latency Timer Addressable as byte Power on reset value xxH Bit(s) R/W Name 7:3 R/W LATENCY 2:0 R ...
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ENSONIQ Proprietary Information Subsystem Vendor ID Addressable as word Power on reset value 1274H Bit(s) R/W Name 15:0 R SUBSYSTEM VENDOR ID Subsystem ID Addressable as word Power on reset value 1371H Bit(s) R/W Name 15:0 R SUBSYSTEM ID Expansion ...
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ENSONIQ Proprietary Information Max_Lat Addressable as byte Power on reset value 80H Bit(s) R/W Name 7:0 R MAX_LAT Capabilities Identifier Addressable as byte Power on reset value 01H Bit(s) R/W Name 7:0 R CAP_ID Next Item Pointer Addressable as byte ...
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ENSONIQ Proprietary Information Power Management Control/Status - PMCSR Addressable as byte, word or long word Power on reset value 00000001H Bit(s) R/W Name 15 R/W PME_Status clear 14:13 R Not Implemented 12:9 R Not Implemented 8 R/W PME_En 7:2 R ...
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ENSONIQ Proprietary Information 7.1. IRQ & Chip Select Block The IRQ/Chip Select block contains two 32 bit registers. The first register is the control register which can be read and written. The second register is the status register which is ...
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ENSONIQ Proprietary Information 7 R/W BREQ 6 R/W DAC1_EN 5 R/W DAC2_EN 4 R/W ADC_EN 3 R/W UART_EN 2 R/W JYSTK_EN 1 R/W XTALCKDIS 0 R/W PCICLKDIS ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997 This bit controls access ...
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ENSONIQ Proprietary Information Interrupt/Chip Select Status Register Addressable as longword only Power on reset value 7FFFFEC0H Bit(s) R/W Name 31 R INTR 30:9 R ONES 8 R SYNC_ERR 7:6 R VC[1: MPWR 4 R MCCB 3 R UART ...
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ENSONIQ Proprietary Information 7.2. UART The UART contains three 8 bit registers. The data register can be read or written and is used to receive or transmit MIDI information. The second register bit control register which is ...
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ENSONIQ Proprietary Information UART Control Register Addressable as byte only Power on reset value 00H Bit(s) R/W Name 15 W RXINTEN 14:13 W TXINTEN[1:0] 12:10 UNDEFINED 9:8 W CNTRL[1:0] UART Reserved Register Addressable as byte only Power on reset value ...
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ENSONIQ Proprietary Information 7.4. Sample Rate Converter This block receives or sends samples from/to the serial interface block for the playback/record channels. It also provides the necessary sample rate conversion for the AC97 CODEC. The Sample Rate Converter block contains ...
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ENSONIQ Proprietary Information 7.5. CODEC Interface The CODEC interface register bit register that provides access to the AC97 CODEC control registers. This register is a pseudo read/write and must be accessed as a longword. A write to ...
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ENSONIQ Proprietary Information 7.6. Legacy The Legacy register bit register that performs both control and status functions. Basically the lower word functions as the status register and the upper word functions as the control register. The only ...
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ENSONIQ Proprietary Information 18 R/W SBCAP 17 R/W CDCCAP 16 R/W BACAP 15:11 R ONE 10:8 R E2, E1, E0 7:3 R A[4: W ZERO 0 R/W INT# ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, ...
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ENSONIQ Proprietary Information 7.7. Serial Interface There is one 16 bit control register and three 32 bit control/status registers in the serial block. The 16 bit control register can be read or written. The three 32 bit control/status registers can ...
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ENSONIQ Proprietary Information 10 R/W R1_INT_EN 9 R/W P2_INTR_EN 8 R/W P1_INTR_EN 7 R/W P1_SCT_RLD 6 R/W P2_DAC_SEN 5:4 R/W R1_S_EB : R1_S_MB 3:2 R/W P2_S_EB : P2_S_MB 1:0 R/W P1_S_EB : P1_S_MB ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct ...
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ENSONIQ Proprietary Information DAC1 Channel Sample Count Register Addressable as word, longword Power on reset value 00000000H Bit(s) R/W Name 31:16 R CURR_SAMP_CT 15:0 R/W SAMP_CT DAC2 Channel Sample Count Register Addressable as word, longword Power on reset value 00000000H ...
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ENSONIQ Proprietary Information 7.8. Host Interface - Memory The top 64 bytes of memory are actually used as register storage for the CCB block and also as the FIFO for the UART block. The CCB registers are located in the ...
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ENSONIQ Proprietary Information ADC Frame Register 1 Addressable as longword Power on reset value xxxxxxxxH Bit(s) R/W Name 31:0 R/W PCI ADDRESS ADC Frame Register 2 Addressable as longword Power on reset value xxxxxxxxH Bit(s) R/W Name 31:16 R/W Current ...
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ENSONIQ Proprietary Information 8. POWER MANAGEMENT All power management of the system is under software control. The AC97 CODEC and AudioPCI 97 can be powered down separately. Neither chip loses register information when powered down. The AudioPCI 97 can be ...
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ENSONIQ Proprietary Information 9. PCI BUS Description and Signals AudioPCI 97 is designed to adhere to the PCI Local Bus Specification Revision 2.2, as such it complies with all requirements for bus master capability bit device ...
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... AudioPCI 97 supplies interrupt support for all possible interrupt configurations. This is done so that the greatest possible flexibility can be achieved during the configuration process. PME# Power Management Enable. This signal is not implemented in the ES1371 output only and will be set high. It should be left connect board. 10.2. AC97 CODEC Interface SDATAOUT ...
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ENSONIQ Proprietary Information 10.3. Miscellaneous JYSTK[7:0] Joystick and Button inputs MIDI_OUT Serial output for MIDI compatible communications MIDI_IN Serial input for MIDI compatible communications XTALI/O Crystal input and output XTALOBUF Crystal output buffered (for connection to AC97 CODEC) GPIO[3:0] General ...
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... VSS 17 TRDY# 18 DEVSEL# 19 STOP# 20 SERR# 21 PAR 22 CBE1# 23 AD15 24 VDD 25 VSS 26 AD14 27 AD13 28 AD12 29 AD11 30 ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997 ENSONIQ AC97 ES1371 ENSONIQ Proprietary Information 33 80 VSS 79 JYSTK0 78 JYSTK1 77 JYSTK2 76 JYSTK3 75 VSS 74 VDD 73 JYSTK4 72 JYSTK5 71 JYSTK6 70 JYSTK7 69 MIDI_OUT 68 MIDI_IN 67 VSS ...
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ENSONIQ Proprietary Information 12. TIMING. AudioPCI 97 is being designed to conform to the PCI Local Bus Specification Revision 2.2. Since AudioPCI 97 has a high speed intermediate 8 LWORD RAM buffer, the design target is to have no wait ...
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ENSONIQ Proprietary Information 14. Mechanical Information ENSONIQ AudioPCI 97 Specification Rev 1.1 Oct 1, 1997 ENSONIQ Proprietary Information 35 ...
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ENSONIQ Proprietary Information QFP 100 Plastic Package 100 Pin Flat Pack MILLIMETERS DIM MIN MAX A 23.65 24.15 B 19.90 20.10 C 13.90 14.10 D 17.65 18.15 E 0.65 0.65 F 0.20 ...
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ENSONIQ Proprietary Information 15. APPENDIX 15.1. Bus Latency Since each audio channel has a 64 byte buffer, the Latency requirement for the PCI bus can be calculated as follows: For 8 bit audio: 32 Samples (one half buffer) @ 44.1 ...