SII3132CNU Silicon image, SII3132CNU Datasheet - Page 7

• Manufacturer Part Number: SII3132CNU
• Manufacturer: Silicon image

SiI3132 PCI Express to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
List of Tables
Table 1. Absolute Maximum Ratings .............................................................................................................. 2
Table 2. DC Specifications.............................................................................................................................. 2
Table 3. SATA Interface DC Specifications ..................................................................................................... 3
Table 4. PCI Express Interface DC Specifications ......................................................................................... 3
Table 5. SATA Interface Timing Specifications ............................................................................................... 4
Table 6. SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gbit/s................................................ 4
Table 7. SATA Interface Transmitter Output Jitter Characteristics, 3 Gbit/s ................................................... 5
Table 8. PCI Express Interface Timing Specifications .................................................................................... 5
Table 9. PCI Express Interface Transmitter Output Jitter Characteristics ...................................................... 5
Table 10. CLKI SerDes Reference Clock Input Requirement ........................................................................ 6
Table 11. Power Supply Noise Requirement .................................................................................................. 6
Table 12. SiI3132 Pin Listing .......................................................................................................................... 7
Table 13. Pin Types ........................................................................................................................................ 8
Table 14. PCI Express Pin Descriptions....................................................................................................... 10
2
Table 15. Flash / I
C / LED Pin Descriptions ................................................................................................ 10
Table 16. Serial ATA Signal Pin Descriptions ............................................................................................... 10
Table 17. Test Pin Descriptions .................................................................................................................... 11
Table 18. Power/Ground Pin Descriptions.................................................................................................... 11
Table 19. Package Dimensions .................................................................................................................... 12
Table 20. Scatter/Gather Entry (SGE ........................................................................................................... 17
Table 21. Scatter/Gather Table (SGT ........................................................................................................... 18
Table 22. Control Field Bit Definitions .......................................................................................................... 19
Table 23. Protocol Override Bit Definitions................................................................................................... 20
Table 24. Port Request Block for Standard ATA Command ......................................................................... 20
Table 25. PRB FIS Area Definition................................................................................................................ 21
Table 26. Port Request Block for PACKET Command ................................................................................. 22
Table 27. Port Request Block for Soft Reset Command .............................................................................. 23
Table 28. Port Request Block for External Commands ................................................................................ 24
Table 29. Port Request Block For Receiving Interlocked FIS ...................................................................... 25
Table 30. Interrupt Steering .......................................................................................................................... 29
Table 31. Port Interrupt Causes and Control ................................................................................................ 31
Table 32. Auto-Initialization from Flash Timing ............................................................................................. 35
Table 33. Flash Data Description.................................................................................................................. 35
Table 34. Auto-Initialization from EEPROM Timing ...................................................................................... 36
Table 35. Auto-Initialization from EEPROM Timing Symbols ....................................................................... 36
Table 36. EEPROM Data Description........................................................................................................... 37
Table 37. SiI3132 PCI Configuration Space ................................................................................................. 38
Table 38. SiI3132 Internal Register Space – Base Address 0...................................................................... 54
Table 39. SiI3132 Internal Register Space – Base Address 1...................................................................... 61
Table 40. Port LRAM layout.......................................................................................................................... 62
Table 41. Port LRAM Slot layout................................................................................................................... 62
Table 42. Command Error Codes................................................................................................................. 68
Table 43. Default FIS Configurations............................................................................................................ 70
Table 44. SError Register Bits (DIAG Field) ................................................................................................. 76
Table 45. SiI3132 Internal Register Space – Base Address 2...................................................................... 77
Table 46. Power Management Register Bits ................................................................................................ 79
SiI-DS-0138-D
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© 2007 Silicon Image, Inc.