THC63LVD824 THine Electronics,Inc., THC63LVD824 Datasheet

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THC63LVD824

Manufacturer Part Number
THC63LVD824
Description
Manufacturer
THine Electronics,Inc.
Datasheet

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THC63LVD824
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Part Number:
THC63LVD824
Manufacturer:
THINE
Quantity:
1 000
Part Number:
THC63LVD824
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THC63LVD824 _Rev2.0
General Description
The THC63LVD824 receiver is designed to support
Single Link transmission between Host and Flat Panel
Display up to SXGA+ resolutions and Dual Link trans-
mission between Host and Flat Panel Display up to
UXGA resolutions. The THC63LVD824 converts the
LVDS data streams back into 48bits of CMOS/TTL data
with falling edge or rising edge clock for convenient
with a variety of LCD panel controllers.
In Single Link, data transmit clock frequency of
135MHz, 48bits of RGB data are transmitted at an
effective rate of 945Mbps per LVDS channel. Using a
135MHz clock, the data throughput is 472Mbytes per
second.
In Dual Link, data transmit clock frequency of 85MHz,
48bits of RGB data are transmitted at an effective rate
of 595Mbps per LVDS channel. Using a 85MHz clock,
the data throughput is 595Mbytes per second.
Block Diagram
Copyright 2000-2003 THine Electronics, Inc. All rights reserved
Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA
2nd Link
1st Link
(25 to 135MHz)
(25 to 85MHz)
LVDS INPUT
RCLK1 +/-
RCLK2 +/-
RA1 +/-
RB1 +/-
RA2 +/-
RB2 +/-
/PDWN
RC1 +/-
RD1 +/-
RC2 +/-
RD2 +/-
R/F
THC63LVD824
PLL
PLL
28
28
Features
1
Wide dot clock range: 25-170MHz suited for VGA,
SVGA, XGA, SXGA, SXGA+ and UXGA
PLL requires No external components
Supports Single Link up to 135MHz dot clock for
SXGA+
Supports Dual Link up to 170MHz dot clock for
UXGA
50% output clock duty cycle
TTL clock edge programmable
TTL output driverbility selectable for lower EMI
Power down mode
Low power single 3.3V CMOS design
100pin TQFP
THC63LVDF84B compatible
8
8
8
8
8
8
RED1
GREEN1
BLUE1
RED2
GREEN2
BLUE2
HSYNC
VSYNC
DE
RECEIVER CLOCK OUT
(25 to 85MHz)
CMOS/TTL OUTPUT
1st DATA
2nd DATA
THine Electronics, Inc.

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THC63LVD824 Summary of contents

Page 1

... THC63LVD824 _Rev2.0 Single(135MHz)/Dual(170MHz) Link LVDS Receiver for XGA/SXGA/SXGA+/UXGA General Description The THC63LVD824 receiver is designed to support Single Link transmission between Host and Flat Panel Display up to SXGA+ resolutions and Dual Link trans- mission between Host and Flat Panel Display up to UXGA resolutions ...

Page 2

... THC63LVD824 _Rev2.0 Pin Out LVDS GND 76 RA1- 77 RA1+ 78 RB1- 79 RB1+ 80 LVDS VCC 81 RC1- 82 RC1+ 83 RCLK1- 84 RCLK1+ 85 RD1- 86 RD1+ 87 LVDS GND 88 RA2- 89 RA2+ 90 RB2- 91 RB2+ 92 LVDS VCC 93 RC2- 94 RC2+ 95 RCLK2- 96 RCLK2+ 97 RD2- 98 RD2+ 99 LVDS GND 100 Copyright 2000-2003 THine Electronics, Inc. All rights reserved ...

Page 3

... THC63LVD824 _Rev2.0 Pin Description Pin Name Pin # RA1+, RA1- 78, 77 RB1+, RB1- 80, 79 RC1+, RC1- 83, 82 RD1+, RD1- 87, 86 RCLK1+, RCLK1- 85, 84 RA2+, RA2- 90, 89 RB2+, RB2- 92, 91 RC2+, RC2- 95, 94 RD2+, RD2- 99, 98 RCLK2+, RCLK2- 97, 96 52, 51, 50, 47, R17 ~ R10 ...

Page 4

... THC63LVD824 _Rev2.0 Pin Name Pin # PLL VCC 2 PLL GND 1 Absolute Maximum Ratings Supply Voltage ( CMOS/TTL Input Voltage CMOS/TTL Output Voltage LVDS Receiver Input Voltage Output Current Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10sec) Maximum Power Dissipation @+25 Electrical Characteristics ...

Page 5

... THC63LVD824 _Rev2.0 Supply Current Symbol Parameter Receiver Supply I Current RCCG (256 Gray Scale Pattern) Receiver Supply I Current RCCW (Double Checker Pattern) Receiver Power Down I RCCS Supply Current Copyright 2000-2003 THine Electronics, Inc. All rights reserved V = 3.0V ~ 3.6V -10 CC Condition(*) MODE<1:0>=LH VESA SXGA (60Hz), ...

Page 6

... THC63LVD824 _Rev2.0 256 Gray Scale Pattern CLKOUT Rx0/Gx0/Bx0 Rx1/Gx1/Bx1 Rx2/Gx2/Bx2 Rx3/Gx3/Bx3 Rx4/Gx4/Bx4 Rx5/Gx5/Bx5 Rx6/Gx6/Bx6 Rx7/Gx7/Bx7 x=1,2 DE Double Checker Pattern CLKOUT R1n/G1n/B1n R2n/G2n/B2n n=0~7 DE Copyright 2000-2003 THine Electronics, Inc. All rights reserved 6 THine Electronics, Inc. ...

Page 7

... THC63LVD824 _Rev2.0 Switching Characteristics Symbol Parameter Dual-in / Dual-out t CLKOUT Period RCP Single-in / Dual-out t CLKOUT High Time RCH t CKLOUT Low Time RCL t TTL Data Setup to CLKOUT RS t TTL Data Hold from CKLOUT RH t TTL Low to High Transition Time TLH t TTL High to Low Transition Time ...

Page 8

... THC63LVD824 _Rev2.0 AC Timing Diagrams TTL Outputs 2.0V CLKOUT Rxn Gxn Bxn 0~7 Phase Lock Loop Set Time VCC RCLKx+/- /PDWN CLKOUT Copyright 2000-2003 THine Electronics, Inc. All rights reserved t RCH 2.0V 2.0V t RCP t RS 2.0V 2.0V 0.8V 0.8V 3.0V 2. RCL R 0.8V 0.8V R RPLL 2.0V THine Electronics, Inc. ...

Page 9

... THC63LVD824 _Rev2.0 Pixel Map Table for Single/Dual Link 1st Pixel Data 824 TTL Output Pin R10 LSB R11 R12 R13 R14 R15 R16 R17 MSB G10 LSB G11 G12 G13 G14 G15 G16 G17 MSB B10 LSB B11 B12 B13 B14 ...

Page 10

... THC63LVD824 _Rev2.0 824 TTL Data Output Timing for Single/Dual Link Example : SXGA+(1400 x 1050) HSYNC DE CLKOUT R1x/G1x/B1x R2x/G2x/B2x n = 0~7 Copyright 2000-2003 THine Electronics, Inc. All rights reserved # 1395 #1397 # 1396 #1398 #1 #2 #1399 TFT Panel (1400 x 1050) 10 #1399 ...

Page 11

... THC63LVD824 _Rev2.0 AC Timing Diagrams LVDS Inputs Ryx+/- Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 Ryx0 Ryx6 Ryx5 Ryx4 Ryx3 Ryx2 Ryx1 RCLKx 1 A,B,C,D RCLK1+ t RCLK2+ Copyright 2000-2003 THine Electronics, Inc. All rights reserved t RIP2 t RIP3 t RIP4 t RIP5 t RIP6 t RIP0 t RIP1 diff ...

Page 12

... THC63LVD824 _Rev2.0 LVDS Data Inputs Timing Diagrams in Single Link Previous Cycle (2nd pixel data) RCLK1+ RA1+/- R26’ R25’ R24’ RB1+/- G27’ G26’ G25’ RC1+/- B27’ B26’ HSYNC’ RD1+/- B20’ G21’ ...

Page 13

... THC63LVD824 _Rev2.0 LVDS Data Inputs Timing Diagrams in Dual Link Previous Cycle RCLK1+ RA1+/- R16’ R15’ R14’ RB1+/- G17’ G16’ G15’ RC1+/- B17’ B16’ HSYNC’ RD1+/- B10’ G11’ G10’ RCLK2+ RA2+/- R26’ ...

Page 14

... THC63LVD824 _Rev2.0 Package INDEX ∆ 100 PIN No.1 0.5TYP 0. Copyright 2000-2003 THine Electronics, Inc. All rights reserved UNITS:mm THine Electronics, Inc. ...

Page 15

... Judgment on whether THC63LVD824 comes under strategic products prescribed by the Foreign Exchange and For- eign Trade Control Law is the user’s responsibility. 8. This technical document was provisionally created during development of THC63LVD824, so there is a possibility of differences between it and the product’s final specifications. When designing circuits using THC63LVD824, be sure to refer to the final technical documents ...

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