GM5110 GMI, GM5110 Datasheet
GM5110
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GM5110 Summary of contents
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... XGA/SXGA LCD Controller *** Genesis Microchip Confidential *** NOTE: Sections in this data sheet that mention HDCP apply only to the HDCP-enabled chip versions (gm5110-H and gm5120-H). All other sections apply to all chip versions (gm5110, gm5110-H, gm5120, and gm5120-H). Publication number: C5110-DAT-01C 2150 Gold Street, Alviso, P.O. Box 2150, CA USA 95002 Tel: (408) 262-6599 Fax: (408) 262-6365 165 Commerce Valley Dr ...
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... Changes to Table 22– Maximum Speed of Operation: – Renamed parameters P – Renamed parameters I – Added note (6). • Removed the clock speed column from section 6 - Ordering Information and added the ordering information for gm5110-H and gm5120-H. • Pins 143 ~ 146: changed xxx_SDDS or xxxx_SDDS to xxx_DDDS or xxxx_DDDS D5110-DAT-01C respectively • ...
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... Genesis Microchip Inc. reserves the right to change or modify the information contained herein without notice. Please obtain the most recent revision of this document. Genesis Microchip Inc. makes no warranty for the use of its products and bears no responsibility for any errors or omissions that may appear in this document. gm5110/20 Preliminary Data Sheet ...
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... Genesis Microchip Confidential *** 1. Overview ............................................................................................................................................ 1 1.1 gm5110/20 System Design Example ........................................................................................... 1 1.2 gm5110/20 Features..................................................................................................................... 2 2. gm5110/20 Pinout .............................................................................................................................. 3 3. gm5110/20 Pin List ............................................................................................................................ 4 4. Functional Description ..................................................................................................................... 10 4.1 Clock Generation ....................................................................................................................... 10 4.1.1 Using the Internal Oscillator with External Crystal............................................................ 11 4.1.2 Using an External Clock Oscillator .................................................................................... 13 4.1.3 Clock Synthesis................................................................................................................... 14 4.2 Hardware Reset .......................................................................................................................... 16 4.3 Analog to Digital Converter....................................................................................................... 16 4 ...
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... Host Interface........................................................................................................................... 36 4.16.1 Host Interface Command Format...................................................................................... 37 4.16.2 2-wire Serial Protocol ....................................................................................................... 37 4.17 Miscellaneous Functions.......................................................................................................... 39 4.17.1 Low Power State............................................................................................................... 39 4.17.2 Pulse Width Modulation (PWM) Back Light Control ...................................................... 39 5. Electrical Specifications ................................................................................................................... 40 5.1 Preliminary DC Characteristics ................................................................................................. 40 5.2 Preliminary AC Characteristics ................................................................................................. 41 6. Ordering Information ....................................................................................................................... 43 7. Mechanical Specifications................................................................................................................ 44 June 2002 gm5110/20 Preliminary Data Sheet iv C5110-DAT-01C ...
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... Core Power and Ground Pins.................................................................................9 Table 13. TCLK Specification .............................................................................................14 Table 14. Pin Connection for RGB Input with HSYNC/VSYNC .......................................17 Table 15. ADC Characteristics ............................................................................................18 Table 16. DVI Receiver Characteristics ..............................................................................20 Table 17. gm5110/20 GPIOs and Alternate Functions ........................................................35 Table 18. Bootstrap Signals .................................................................................................36 Table 19. Instruction Byte Map ...........................................................................................37 Table 20. Absolute Maximum Ratings ................................................................................40 Table 21. DC Characteristics ...............................................................................................41 Table 22. ...
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... Internally Synthesized Clocks..............................................................................15 Figure 9. On-chip Clock Domains ......................................................................................16 Figure 10. Example ADC Signal Terminations.....................................................................17 Figure 11. gm5110/20 Clock Recovery.................................................................................18 Figure 12. ADC Capture Window .........................................................................................19 Figure 13. Some of gm5110/20 built-in test patterns ............................................................21 Figure 14. HSYNC Delay......................................................................................................22 Figure 15. Active Data Crosses HSYNC Boundary ..............................................................23 Figure 16. ODD/EVEN Field Detection................................................................................24 TM Figure 17. RealColor Digital Color Controls ...
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... Figure 1 below shows a typical dual interface LCD monitor system based on the gm5110/20. Designs based on the gm5110/20 have reduced system cost, simplified hardware and firmware design and increased reliability because only a minimal number of components are required in the system. Analog RGB ...
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... ROM (configuration settings stored in NVRAM) • Programmable Output Format • Single / double wide up to XGA 75Hz output for gm5110 and up to SXGA 75Hz output for gm5120 • Pin swap, odd / even swap and red / blue group swap of RGB outputs for flexibility in board layout • ...
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... Genesis Microchip Confidential *** gm5110 and gm5120 are pin-compatible. These devices are available in a 208-pin Plastic Quad Flat Pack (PQFP) package. Figure 2 provides the pin locations for all signals. Figure 2. GPIO17 1 RVDD 2 RVSS 3 GPIO21/IRQn 4 RESETn 5 GPIO14/DDC_SCL 6 GPIO15/DDC_SDA 7 ROM_ADDR15 8 ROM_ADDR14 9 ROM_ADDR13 10 ROM_ADDR12 ...
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... G VDD2_ADC_2.5 153 P June 2002 gm5110/20 Preliminary Data Sheet Analog Input Port Description Analog power (3.3V) for the red channel. Must be bypassed with decoupling capacitor to AGND_RED pin on system board (as close as possible to the pin). Positive analog input for Red channel. Negative analog input for Red channel. ...
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... CMOS/TTL clock oscillator (refer to Figure 7). This is a 5V-tolerant input. XTAL 151 AO Crystal oscillator output. VDD_RPLL 148 P Digital power for RCLK PLL. Connect to 3.3V supply. VSS_RPLL 147 G Digital ground for RCLK PLL. June 2002 gm5110/20 Preliminary Data Sheet Table 2. DVI Input Port Table 3. RCLK PLL Pins 5 C5110-DAT-01C ...
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... Schmitt trigger (400mV typical hysteresis), 5V-tolerant] GPO0 119 O General-purpose output signals. GPO1 120 O GPO2 121 O GPO3 122 O GPO4 123 O GPO5 124 O GPO6 125 O GPO7 126 O June 2002 gm5110/20 Preliminary Data Sheet Analog HSYNC/VSYNC Inputs System Interface and GPIO Signals 6 C5110-DAT-01C ...
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... O PD14 71 O PD13 70 O PD12 69 O PD11 66 O PD10 65 O PD9 64 O PD8 63 O PD7 62 O PD6 61 O PD5 60 O PD4 59 O PD3 58 O PD2 57 O PD1 56 O PD0 55 O June 2002 gm5110/20 Preliminary Data Sheet Display Output Port 7 C5110-DAT-01C ...
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... External PROM data Output Enable Pin Name No I/O Description N/C 127 O No connect. N/C 128 O No connect. Reserved 131 I Tie to GND. Reserved 132 I Tie to GND. N/C 142 O No connect. N/C 200 O No connect. June 2002 gm5110/20 Preliminary Data Sheet Parallel ROM Interface Port Table 8. Reserved Pins 8 C5110-DAT-01C ...
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... Table 12. Core Power and Ground Pins Pin Name No I/O Description CVDD_2 Connect to 2.5V supply Must be bypassed with a 0.1uF capacitor to CVSS (as close to the pin as possible). 134 P 203 P CVSS 27 G Connect to digital ground 133 G 135 G 202 G June 2002 gm5110/20 Preliminary Data Sheet 9 C5110-DAT-01C ...
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... The gm5110/20 features three clock inputs. All additional clocks are internal clocks derived from one or more of these: 1. Crystal Input Clock (TCLK and XTAL). This is the input pair to an internal crystal oscillator and corresponding logic. A 14.3 MHz TV crystal is recommended. Other crystal frequencies may be used, but require custom programming. This is illustrated in Figure 4 below ...
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... The oscillator circuit also minimizes the overdrive of the crystal, which reduces the aging of the crystal. When the gm5110/ reset, the state of the ROM_ADDR13 pin (pin number 10) is sampled. If the pin is left unconnected (internal pull-down) then internal oscillator is enabled. ...
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... Figure 6. The loading capacitance (C on the crystal is the combination The shunt capacitance shunt XTAL and TCLK pins. For the gm5110/20 this is approximately 9 pF. C parallel combination of the external loading capacitors ( the pin capacitance (C pcb capacitance (C ). The capacitances are symmetrical so that C esd ...
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... Using an External Clock Oscillator Another option for providing the reference clock is to use a single-ended external clock oscillator. When the gm5110/ reset, the state of the ROM_ADDR13 (pin 10) is sampled. If ROM_ADDR13 is pulled high by connecting to VDD through a pull-up resistor (15KΩ recommended, 15KΩ maximum) then external oscillator mode is enabled. In this mode the internal oscillator circuit is disabled and the external oscillator signal that is connected to the TCLK pin (pin number 152) is routed to an internal clock buffer ...
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... Maximum Duty Cycle Table 13. TCLK Specification 4.1.3 Clock Synthesis The gm5110/20 synthesizes all additional clocks internally as illustrated in Figure 8 below. The synthesized clocks are as follows: 1. Main Timing Clock (TCLK) is the output of the chip internal crystal oscillator. TCLK is derived from the TCLK/XTAL pad input. ...
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... Source Timing Measurement Domain Clock (IFM_CLK). Max = 50MHz 5. ADC Domain Clock (ACLK). Max = 165MHz. The clock selection for each domain as shown in the figure below is controlled using the CLOCK_CONFIG registers (index 0x03 and 0x04). June 2002 gm5110/20 Preliminary Data Sheet SDDS IP_CLK DDDS /2 ...
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... The gm5110/20 chip has three ADC’s (analog-to-digital converters), one for each color (red, green, and blue). June 2002 gm5110/20 Preliminary Data Sheet ...
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... Genesis Microchip Confidential *** 4.3.1 ADC Pin Connection The analog RGB signals are connected to the gm5110/20 as described below: Table 14. Pin Connection for RGB Input with HSYNC/VSYNC Pin Name Red+ Red Red- Terminate as illustrated in Figure 10 Green+ Green Green- Terminate as illustrated in Figure 10 Blue+ Blue ...
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... No Missing Codes Integral Non-Linearity (INL) Channel to Channel Matching The gm5110/20 ADC has a built in clamp circuit for AC-coupled inputs. By inserting series capacitors (about 10 nF), the DC offset of an external video source can be removed. The clamp pulse position and width are programmable. 4.3.3 Clock Recovery Circuit The SDDS (Source Direct Digital Synthesis) clock recovery circuit generates the clock used to sample analog RGB data (IP_CLK or source clock) ...
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... IP_CLKs (equivalent to a pixel count). In the vertical direction it is defined in lines. All the parameters beginning with “Source” are programmed gm5110/20 registers values. Note that the input vertical total is solely determined by the input and is not a programmable parameter ...
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... Genesis Microchip Confidential *** For ADC interlaced inputs, the gm5110/20 may be programmed to automatically determine the field type (even or odd) from the VSYNC/HSYNC relative timing. See Input Format Measurement, Section 4. ...
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... The gm5110/20 contains hundreds of test patterns, some of which are shown in Figure 13. Once programmed, the gm5110/20 test pattern generator can replace a video source (e.g. a PC) during factory calibration and test. This simplifies the test procedure and eliminates the possibility of image noise being injected into the system from the source. The foreground and background colors are programmable ...
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... Delayed horizontal sync may be used to solve a potential problem with VSYNC jitter with respect to HSYNC. VSYNC and HSYNC are generally driven active coincidentally, but with different paths to the gm5110/20 (HSYNC is often regenerated from a PLL result, VSYNC may be seen earlier or later. Because VSYNC is used to reset the line ...
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... An interrupt can also be programmed to occur. June 2002 gm5110/20 Preliminary Data Sheet active data crosses HS boundary delayed HS placed safely within blanking Active Data Crosses HSYNC Boundary ...
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... VS - even VS - odd Figure 16. 4.6.6 Input Pixel Measurement The gm5110/20 provides a number of pixel measurement functions intended to assist in configuring system parameters such as pixel clock, SDDS sample clocks per line and phase setting, centering the image, or adjusting the contrast and brightness. 4.6.7 Image Phase Measurement This function measures the sampling phase quality over a selected active window region. ...
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... Genesis Microchip Confidential *** 4.6.8 Image Boundary Detection The gm5110/20 performs measurements to determine the image boundary. This information is used when programming the Active Window and centering the image. 4.6.9 Image Auto Balance The gm5110/20 performs measurements on the input data that is used to adjust brightness and contrast ...
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... For example, this allows SXGA 1280 pixels to be displayed as 1024 (XGA). The gm5110/20 provides an arbitrary vertical shrink down to (50 line) of the original image size. Together with the arbitrary horizontal shrink, this allows the gm5110/20 to capture and display images one VESA standard format larger than the native display resolution ...
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... The gm5110/20 provides 10-bit look-up table (LUT) for each input color channel intended for Gamma correction and to compensate for a non-linear response of the LCD panel. A 10-bit output results in an improved color depth control. The 10-bit output is then dithered down to 8 bits (or 6 bits) per channel at the display (see section 4.11.3 below). The LUT is user programmable to provide an arbitrary transfer function ...
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... Display Background Window Display Active Window Vertical Blanking (Front Porch) DHS DEN ** DH_HS_END DH_ACTIVE_WIDTH DH_ACTIVE_START Figure 18. The double-wide output only supports an even number of horizontal pixels. June 2002 gm5110/20 Preliminary Data Sheet DH_BKGND_END VSYNC Region DH_TOTAL ** Display Windows and Timing 28 DV_VS_END DV_BKGND_START DV_ACTIVE_START DV_ACTIVE_LENGTH ...
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... OR/OG/OB (Output) Figure 20. 4.11.3 Panel Power Sequencing (PPWR, PBIAS) gm5110/20 has two dedicated outputs PPWR and PBIAS (pins 113 and 114) to control LCD power sequencing once data and control signals are stable. The timing of these signals is fully programmable. TMG1 PPWR Output Panel Data and Control Signals PBIAS Output < ...
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... High spikes in the EMI power spectrum may cause LCD monitor products to violate emissions standards. The gm5110/20 has many features that can be used to reduce electromagnetic interference (EMI). These include drive strength control and clock spectrum modulation. These features help to eliminate the costs associated with EMI reducing components and shielding ...
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... For example, an OSD menu 360 pixels wide by 360 pixels high is 30 cells in width and 20 cells in height. Many of these cells would be the same (e.g. empty). In this case, the menu June 2002 gm5110/20 Preliminary Data Sheet CELLMAP_XSZ Brightness Contrast Figure 22 ...
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... The gm5110/20 on-chip microcontroller (OCM) serves as the system microcontroller. It programs the gm5110/20 and manages other devices in the system such as the keypad, the back light and non-volatile RAM (NVRAM) using general-purpose input/output (GPIO) pins. The OCM can operate in two configurations, Standalone configuration and Full-Custom configuration, as illustrated in Figure 23 ...
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... Standalone configuration offers the most simple and inexpensive system solution for generic LCD monitors. In this configuration the OCM executes firmware stored internally in gm5110/20. This is illustrated in Figure 23A. The on-chip firmware provides all the standard functions required in a high-quality generic LCD monitor. This includes mode-detection, auto-configuration and a high-quality standard OSD menu system ...
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... ROM or programmable Flash ROM devices. Normally 64KB or 128KB of ROM is required. Both instructions and data are fetched from external ROM on a cycle-by-cycle basis. The speed of the accesses on the parallel port is determined by the gm5110/20 internal OCM_CLK. This in turn determines the speed of the external ROM device. For example ...
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... OCM external interrupt source (IRQINn). Write enable for external ROM if programmable FLASH device is used. Data and clock lines for master 2-wire serial interface to NVRAM when gm5110/20 is used in standalone configuration (section Figure 23). Clock and data lines for 2-wire serial interface connected to the Direct Data Channel (DDC) of the DVI input, for passing HDCP keys ...
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... A serial host interface is provided to allow an external device to peek and poke registers in the gm5110/20. This is done using a 2-wire serial protocol. Note that 2-wire host interface requires bootstrap settings as described in Table 18. The 2-wire host interface is suitable for connection to a factory interrogation port. This is illustrated in Figure 26 ...
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... This is described in Table 19. The first byte of each transfer indicates the type of operation to be performed by the gm5110/20. The table below lists the instruction codes and the type of transfer operation. The content of bytes that follow the instruction byte will vary depending on the instruction chosen ...
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... Increment, the address pointer is automatically incremented after each byte has been sent and written. The transmission data stream for this mode is illustrated in Figure 28 below. The highlighted sections of the waveform represent moments when the transmitting device must release the HFSn line and wait for an acknowledgement from the gm5110/20 (the slave receiver). HCLK ...
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... F u 4.17.1 Low Power State The gm5110/20 provides a low power state in which the clocks to selected parts of the chip may be disabled (see Table 21). 4.17.2 Pulse Width Modulation (PWM) Back Light Control Many of today’s LCD back light inverters require both a PWM input and variable DC voltage to minimize flickering (due to the interference between panel timing and inverter’ ...
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... NOTE (3): Package thermal resistance is based on a PCB with one signal plane and two power planes. Package θ four or more layers NOTE (4): Based on the figures for the Operating Junction Temperature θ calculated as . This equals 104 degrees Celsius for gm5110 and 106 degrees Celsius for gm5120 June 2002 C h ...
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... Genesis Microchip Confidential *** PARAMETER Power Consumption @ 96 MHz (gm5110) Power Consumption @ 135 MHz (gm5120) Power Consumption @ Low Power Mode 3.3V Supply Voltages (AVDD and RVDD) 2.5V Supply Voltages (VDD and CVDD) Supply Current @ CLK = 96 MHz (gm5110) (2) • 2.5V digital supply (3) • 2.5V analog supply (4) • 3.3V digital supply (5) • ...
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... SCL LOW time SDA to SCL Setup SDA from SCL Hold Propagation delay from SCL to SDA Note: The above table assumes OCM_CLK = R_CLK / 2 = 100 MHz (default) (ie 10ns / clock) June 2002 gm5110/20 Preliminary Data Sheet Max Speed of Operation 24 MHz (14.3MHz recommended) 165MHz 162.5MHz 5 MHz 50MHz (14 ...
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... Order Code Application gm5110 XGA (1) gm5110-H XGA gm5120 SXGA (1) gm5120-H SXGA Note (1): gm5110-H and gm5120-H versions will only be sold to HDCP licensed customers. June 2002 gm5110/20 Preliminary Data Sheet Package Temperature Range 208-pin PQFP 0-70°C 208-pin PQFP 0-70°C 208-pin PQFP 0-70°C 208-pin PQFP 0-70° ...
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... Genesis Microchip Confidential *** 7. MECHANICAL SPECIFICATIONS Figure 30. gm5110/gm5120 208-pin PQFP Mechanical Drawing 208 See Detail A Seating Plane Dimension in mm Symbol Min A 3. 0.18 c 0.13 D 27.90 E 27.90 e 0.50 BSC H 30. 30. 0.65 L 1.60 REF June 2002 gm5110/20 Preliminary Data Sheet ...