RTL8139D ETC ETC, RTL8139D Datasheet
RTL8139D
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RTL8139D Summary of contents
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General Description The Realtek RTL8100B( highly integrated, cost-effective single-chip Fast Ethernet controller that provides 32-bit performance, PCI bus master capability, and full compliance with IEEE 802.3u 100Base-T specifications and IEEE 802.3x Full Duplex Flow Control. It also ...
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Pin Assignments 66 GND 67 RXIN- 68 RXIN AVDD 71 TXD- 72 TXD+ 73 GND 74 ISOLATEB 75 AVDD LED2 LED1 80 LED0 81 INTAB 82 RSTB 83 CLK 84 ...
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RTT3 64 LWAKE 65 RTSET 66 GND 67 RXIN- 68 RXIN AVDD 71 TXD- 72 TXD+ 73 GND 74 ISOLATEB 75 AVDD LED2 LED1 80 LED0 81 INTAB 82 RSTB ...
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Pin Description 4.1 Power Management/Isolation Interface Symbol Type PMEB O/D (PME#) ISOLATEB I (ISOLATE#) LWAKE O 4.2 PCI Interface Symbol Type AD31-0 T/S 86,87,89,91-95,100, 1,3-5,8-10,23-30,33, 36-38,41,42,44,45 C/BE3-0 T/S 98,11,21,32 CLK I DEVSELB S/T/S FRAMEB S/T/S 2001-11-9 Pin No 57 ...
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GNTB I REQB T/S IDSEL I INTAB O/D IRDYB S/T/S TRDYB S/T/S PAR T/S PERRB S/T/S SERRB O/D STOPB S/T/S RSTB I 2001-11-9 84 Grant: This signal is asserted low to indicate to the RTL8100B(L) that the central arbiter has ...
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EPROM/EEPROM Interface Symbol Type AUX I EESK O EEDI O EEDO O, I EECS O 4.4 Power Pins Symbol Type VDD P 6,22,34,39,90,97 AVDD P VDD25 P AVDD25 P GND P 2,16,31,43,56, 62,66,73,88 4.5 LED Interface Symbol Type LED0, ...
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Attachment Unit Interface Symbol Type TXD+ O TXD- O RXIN+ I RXIN 4.7 Test and Other Pins Symbol Type RTT3 TEST RTSET I/O VCTRL Analog NC - 7,35,40, 52,53, 54, 69, 76, 78 2001-11-9 ...
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Register Descriptions The RTL8100B(L) provides the following set of operational registers mapped into PCI memory space or I/O space. Offset R/W 0000h R/W 0001h R/W 0002h R/W 0003h R/W 0004h R/W 0005h R/W 0006h-0007h - 0008h R/W 0009h R/W ...
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R/W 0053H - R /W 0054h-0057h 0058h R/W 0059h R/W 005Ah R/W 005Bh - 005Ch-005Dh R/W 005Eh R 005Fh - 0060h-0061h R 0062h-0063h R/W 0064h-0065h R 0066h-0067h R/W 0068h-0069h R 006Ah-006Bh R 006Ch-006Dh R 006Eh-006Fh R 0070h-0071h R/W 0072h-0073h ...
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R/W 00D3h R/W 00D4h-00D7h - 00D8h R/W 00D9h-00FFh - 5.1 Receive Status Register in Rx packet header Bit R 12 ...
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Transmit Status Register (TSD0-3)(Offset 0010h-001Fh, R/W) The read-only bits (CRS, TABT, OWC, CDH, NCC3-0, TOK, TUN) will be cleared by the RTL8100B(L) when the Transmit Byte Count (bits 12-0) in the corresponding Tx descriptor is written not ...
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ERSR: Early Rx Status Register (Offset 0036h, R) Bit R/W 7 5.4 Command Register (Offset 0037h, R/W) This register is used for issuing commands to the RTL8100B(L). These commands are ...
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Interrupt Mask Register (Offset 003Ch-003Dh, R/W) This register masks the interrupts that can be generated from the Interrupt Status Register. A hardware reset will clear all mask bits. Setting a mask bit allows the corresponding bit in the Interrupt ...
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Transmit Configuration Register (Offset 0040h-0043h, R/W) This register defines the Transmit Configuration for the RTL8100B(L). It controls such functions as Loopback, programmable Interframe Gap, Fill and Drain Thresholds, and maximum DMA burst size. Bit R 30-26 R ...
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R/W 3 5.8 Receive Configuration Register (Offset 0044h-0047h, R/W) This register is used to set the receive configuration for the RTL8100B(L). Receive properties such as accepting error packets, runt packets, setting the receive drain threshold etc. ...
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R/W RXFTH2 12-11 R/W 10-8 R/W MXDMA2 R R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 2001-11-9 Rx FIFO Threshold: Specifies Rx FIFO Threshold level. When the number ...
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Command Register (Offset 0050h, R/W) This register is used for issuing commands to the RTL8100B(L). These commands are issued by setting the corresponding bits for the function. A warm software reset along with individual reset and enable/disable ...
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CONFIG 0: Configuration Register 0 (Offset 0051h, R/W) Bit R 4-3 R 2-0 - 5.11 CONFIG 1: Configuration Register 1 (Offset 0052h, R/W) Bit R/W Symbol 7-6 R/W LEDS1-0 5 R/W DVRLOAD 4 ...
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Media Status Register (Offset 0058h, R/W) This register allows configuration of device and PHY options, and provides PHY status information. Bit R/W 7 R 2001-11-9 ...
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CONFIG 3: Configuration Register3 (Offset 0059h, R/W) Bit R R/W 5 R/W 4 R/W 3 2001-11-9 Symbol GNTSel Gnt Select: Select the Frame’s asserted time after the Grant signal has been asserted. The ...
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CONFIG 4: Configuration Register4 (Offset 005Ah, R/W) Bit R/W 7 R/W RxFIFOAutoClr 6 R/W 5 R R/W 2001-11-9 Symbol Set to 1, the RTL8100B(L) will clear the Rx FIFO overflow ...
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Multiple Interrupt Select Register (Offset 005Ch-005Dh, R/W) If the received packet data is not a familiar protocol (IPX, IP, NDIS, etc.) to the RTL8100B(L), RCR<ERTH[3:0]> will not be used to transfer data in early mode. This register will be ...
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Transmit Status of All Descriptors (TSAD) Register (Offset 0060h-0061h, R/W) Bit R ...
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Basic Mode Status Register (Offset 0064h-0065h, R) Bit Name 15 100Base- enable 100Base-T4 support suppress 100Base-T4 support. 14 100Base_TX_ enable 100Base-TX full duplex support suppress 100Base-TX full duplex support. 13 ...
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Auto-Negotiation Advertisement Register (Offset 0066h-0067h, R/W) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-negotiation. Bit Name 15 NP Next Page bit transmitting the protocol specific ...
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Auto-Negotiation Link Partner Ability Register (Offset 0068h-0069h, R) This register contains the advertised abilities of the Link Partner as received during Auto-negotiation. The content changes after the successful Auto-negotiation if Next-pages are supported. Bit Name 15 NP Next Page ...
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Disconnect Counter (Offset 006Ch-006Dh, R) Bit Name 15-0 This 16-bit counter increments by 1 for every disconnect event. It DCNT rolls over when becomes full cleared to zero by read command. 5.24 False Carrier Sense Counter (Offset ...
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CS Configuration Register (Offset 0074h-0075h, R/W) Bit Name Auto-neg speeds up internal timer Testfun 14-10 Reserved - 9 LD Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in ...
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Config5: Configuration Register 5 (Offset 00D8h, R/W) This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no need to enable Config register write prior to writing to Config5. Bit R ...
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EEPROM (93C46) Contents The 93C46 is a 1K-bit EEPROM. Although it is actually addressed by words, its contents are listed below by bytes for convenience. The RTL8100B(L) performs a series of EEPROM read operations from the 93C46 addresses 00H ...
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CONFIG_5 20h-23h TW_PARM_U 24h-27h TW_PARM_T 28h-2Bh PHY1_PARM_T 2Ch PHY2_PARM_T 2Dh-31h - 32h-33h CheckSum 34h-3Eh - 3Fh PXE_Para 40h-7Fh VPD_Data 2001-11-9 Do not change this field without Realtek approval. Bit7-3: Reserved. Bit2: Link Down Power Saving mode: Set to 1: ...
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Summary of the RTL8100B(L) EEPROM Registers Offset Name Type * 00h-05h IDR0 – IDR5 R/W 51h CONFIG0 52h CONFIG1 R LEDS1 * W LEDS1 58h R TxFCE * W TxFCE MSRBMCR 63H 59h ...
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PCI Configuration Space Registers 7.1 PCI Configuration Space Table No. Name Type Bit7 00h VID R 1 01h R 0 02h DID R 0 03h R 1 04h Command 05h 06h ...
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R PME_D3 54h PMCSR 55h R PME_Status W PME_Status 56h–5Fh 60h VPDID R 0 61h NextPtr R 0 62h Flag VPD R/W VPDADDR Address 7 63h R/W Flag 64h VPD Data R/W Data7 65h R/W ...
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PCI Configuration Space Functions The PCI configuration space is intended for configuration, initialization, and catastrophic error handling functions. The functions of RTL8100B(L)'s configuration space are described below. VID: Vendor ID. This field will default to a value of 10ECh ...
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Status: The status register is a 16-bit register used to record status information for PCI bus related events. Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. Bit Symbol 15 ...
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BIST: Built-in Self Test Reads will return a 0, writes are ignored. IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also specifies the number of bytes required as well ...
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Default Values after Power-on (RSTB asserted) No. Name Type 00h VID R 01h R 02h DID R 03h R 04h Command R W 05h R W 06h Status R 07h R W 08h Revision ID R 09h PIFR R ...
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PCI Power Management Functions The RTL8100B(L) is compliant to ACPI (Rev 1.1), PCI Power Management (Rev 1.1), and Device Class Power Management Reference Specification (V1.0a), such as to support an OS Directed Power Management (OSPM) environment. To support this, ...
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The Magic bit (CONFIG3#5) is set to 1, the PMEn bit (CONFIG1#0) is set to 1, and the RTL8100B( isolation state, or the PME# can be asserted in current power state. ♦ The Magic Packet pattern matches, ...
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The RTL8100B(L) also supports the LAN WAKE-UP function. The LWAKE pin is used to notify the motherboard to execute the wake-up process whenever the RTL8100B(L) receives a wakeup event, such as Magic Packet. The LWAKE signal is asserted according the ...
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Block Diagram MAC PCI Interface PHY 10/100 half/full MII Switch Interface Logic TXC10 TXD10 RXC10 RXD10 Transceiver TXC 25M TXD RXC 25M Serial to RXD Parrallel 2001-11-9 EEPROM Interface Power Control Logic Early Interrupt Threshold Register Interrupt Control Early ...
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Functional Description 9.1 Transmit operation The host CPU initiates a transmit by storing an entire packet of data in one of the descriptors in the main memory. When the entire packet has been transferred to the Tx buffer, the ...
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Tx Encapsulation While operating in 100Base-TX mode, the RTL8100B(L) encapsulates the frames that it transmits according to the 4B/5B code-groups table. The changes of the original packet data are listed as follows : 1. The first byte of the ...
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LED Functions 9.12.1 10/100 Mbps Link Monitor The Link Monitor senses the link integrity station is down. 9.12.2 LED_RX In 10/100 Mbps mode, the LED function is like the RTL8139C(L). 9.12.3 LED_TX 2001-11-9 Power On LED ...
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LED_TX+LED_RX 10. Application Diagram RJ45 Magetics 2001-11-9 Power On LED = Low Packet? Yes LED = High for (100 +- 10) ms LED = Low for ( EEPROM LED CLK RTL8100B(L) Auxiliary Power ...
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Electrical Characteristics 11.1 Temperature Limit Ratings Parameter Storage temperature Operating temperature 11.2 DC Characteristics 11.2.1 Supply voltage Vcc = 3.0V min. to 3.6V max. Symbol Parameter V OH Minimum High Level Output Voltage V OL Maximum Low Level Output ...
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AC Characteristics 11.3.1 PCI Bus Operation Timing Target Read Target Write 2001-11-9 50 RTL8100B(L) Rev.1.41 ...
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Configuration Read Configuration Write 2001-11-9 51 RTL8100B(L) Rev.1.41 ...
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BUS Arbitration Memory Read 2001-11-9 52 RTL8100B(L) Rev.1.41 ...
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Memory Write Target Initiated Termination - Retry 2001-11-9 53 RTL8100B(L) Rev.1.41 ...
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Target Initiated Termination - Disconnect Target Initiated Termination - Abort 2001-11-9 54 RTL8100B(L) Rev.1.41 ...
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Master Initiated Termination – Abort Parity Operation - one example 2001-11-9 55 RTL8100B(L) Rev.1.41 ...
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Mechanical Dimensions 12.1 QFP Symbol Dimension in mil Dimension in mm Min Typical Max Min Typical Max A 106.3 118.1 129.9 2.70 4.3 20.1 35.8 0. 102.4 112.2 122.0 2. 7.1 11.8 16.5 0.18 ...
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LQFP Symbol Dimension in inch Dimension in mm Min Nom Max Min - - 0.067 A 0.000 0.004 0.008 0. 0.051 0.055 0.059 1.30 2 0.15 b 0.006 0.009 0.011 0.006 0.008 0.010 0. ...
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Realtek Semiconductor Corp. Headquarters No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2001-11-9 58 RTL8100B(L) Rev.1.41 ...