V53C16128HK45 Mosel-Vitelic, V53C16128HK45 Datasheet

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V53C16128HK45

Manufacturer Part Number
V53C16128HK45
Description
High performance 128K x 16 EDO page mode CMOS dynamic RAM
Manufacturer
Mosel-Vitelic
Datasheet
MOSEL VITELIC
Features
Device Usage Chart
V53C16128H Rev. 1.2 July 1997
HIGH PERFORMANCE
Max. RAS Access Time, (t
Max. Column Address Access Time, (t
Min. Extended Data Out Page Mode Cycle Time, (t
Min. Read/Write Cycle Time, (t
128K x 16-bit organization
EDO Page Mode for a sustained data rate
of 83 MHz
RAS access time: 30, 35, 40, 45, 50 ns
Dual CAS Input
Low power dissipation
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
Refresh Interval: 512 cycles/8 ms
Available in 40-pin 400 mil SOJ and 40/44L-pin
400 mil TSOP-II packages
Single +5V 10% Power Supply
TTL Interface
Temperature
Operating
0 C to 70 C
Range
Package Outline
RAC
K
)
RC
)
V53C16128H
HIGH PERFORMANCE
128K x 16 EDO PAGE MODE
CMOS DYNAMIC RAM
CAA
T
)
PC
30
)
Access Time (ns)
35
30 ns
16 ns
12 ns
65 ns
30
1
Description
performance CMOS dynamic random access
memory. The V53C16128H offers Page mode with
Extended Data Output. EDO Page Mode operation
allows random access up to 256 x 16 bits, within a
page, with cycle times as short as 12ns. An
address, CAS and RAS input capacitances are
reduced to minimize the loading. The V53C16128H
has asymmetric address, 9-bit row and 8-bit
column.
is best suited for graphics, and DSP applications
requiring high performance memories.
40
The V53C16128H is a 131,072 x 16 bit high-
All inputs are TTL compatible. The V53C16128H
45
35 ns
18 ns
14 ns
70 ns
35
50
40 ns
20 ns
15 ns
75 ns
40
Power
Std.
45 ns
22 ns
17 ns
80 ns
45
PRELIMINARY
Temperature
Mark
Blank
50 ns
24 ns
19 ns
90 ns
50

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V53C16128HK45 Summary of contents

Page 1

MOSEL VITELIC V53C16128H HIGH PERFORMANCE 128K x 16 EDO PAGE MODE CMOS DYNAMIC RAM HIGH PERFORMANCE Max. RAS Access Time RAC Max. Column Address Access Time, (t CAA Min. Extended Data Out Page Mode Cycle Time, (t Min. ...

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MOSEL VITELIC Description Pkg. Pin Count SOJ K 40 TSOP-II T 40/44L 40-Pin Plastic SOJ PIN CONFIGURATION Top View Vcc Vcc I/O6 ...

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MOSEL VITELIC Absolute Maximum Ratings* Ambient Temperature Under Bias ................................ – +80 C Storage Temperature (plastic) ..... – +125 C Voltage Relative to V .................–1 +7 Data Output Current ..................................... 50 mA ...

Page 4

MOSEL VITELIC DC and Operating Characteristics 10 Symbol Parameter I Input Leakage Current LI (any input pin) I Output Leakage Current LO (for High-Z State) I ...

Page 5

MOSEL VITELIC AC Characteristics 10 Test conditions, input pulse levels Symbol Parameter 1 t RAS Pulse Width RAS 2 t Read ...

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MOSEL VITELIC AC Characteristics (Cont’d) # Symbol Parameter 30 t Write Command Hold Time from WCR RAS 31 t Write Command to RAS Lead Time RWL 32 t Data in Setup Time Data in Hold Time DH ...

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MOSEL VITELIC Notes dependent on output loading when the device output is selected. Specified I CC output open dependent upon the number of address transitions. Specified I CC transitions per address cycle in EDO ...

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MOSEL VITELIC Truth Table Function RAS Standby H Read: Word L Read: Lower Byte L Read: Upper Byte L Write: Word (Early-Write) L Write: Lower Byte (Early) L Read: Upper Byte (Early) L Read-Write L EDO Page-Mode Read L EDO ...

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MOSEL VITELIC Waveforms of Read Cycle V IH RAS CRP (13 UCAS, LCAS ASR ( ADDRESS ROW ADDRESS ...

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MOSEL VITELIC Waveforms of OE-Controlled Write Cycle V IH RAS CRP (13 UCAS, LCAS CAS ASR ( ADDRESS ROW ADDRESS ...

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MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle V IH RAS CRP (13 UCAS, LCAS ASR ( ROW ADDRESS ADDRESS RCS ( ...

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MOSEL VITELIC Waveforms of EDO Page Mode Read-Write Cycle V IH RAS RCD ( UCAS, LCAS RAD (24 RAH (9) t ASR ( ROW ADDRESS ADD ...

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MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Counter Test Cycle V IH RAS CSR (47 UCAS, LCAS ADDRESS V IL READ CYCLE ...

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MOSEL VITELIC Waveforms of Hidden Refresh Cycle (Read RAS RCD (6) t CRP (13 UCAS, LCAS ASR (8) t RAH ( ROW ADDRESS ADD RCS ...

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MOSEL VITELIC Waveforms of EDO Page Mode Read-Early-Write Cycle (Pseudo Read-Modify-Write RAS CRP RCD V IH UCAS, LCAS RAD t t ASR RAH V IH ROW ADDRESS ADDRESS ...

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MOSEL VITELIC Functional Description The V53C16128H is a CMOS dynamic RAM optimized for high data bandwidth, low power applications functionally similar to a traditional dynamic RAM. The V53C16128H reads and writes data by multiplexing an 17-bit address into ...

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MOSEL VITELIC During a Write cycle goes low at a time in relationship to CAS that would normally cause the outputs to be active necessary to use OE to disable the output drivers prior to the ...

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MOSEL VITELIC Package Outlines 40-Pin Plastic SOJ 1.025 TYP. (1.035 MAX.) [26.04 TYP. (26.29 MAX.)] 40 1 0.1 [2.54] 0.050 0.006 [1.27 0.152] 40/44L-Pin TSOP- 0.0315 BSC [.8001 BSC] 0.039 – 0.047 [0.991 – 1.193] V53C16128H Rev. 1.2 ...

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MOSEL VITELIC V53C16128H Rev. 1.2 July 1997 19 V53C16128H ...

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... MOSEL VITELIC makes no commitment to update or keep cur- rent the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 JAPAN RM ...

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