EM6A9320BI-4MG ETRON Etron Technology, Inc., EM6A9320BI-4MG Datasheet
EM6A9320BI-4MG
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EM6A9320BI-4MG Summary of contents
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... Deleted confidential wording Revision 0.9B(Mar., 2006) Revise the DC and AC characteristics Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EM6A9320BI ...
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... DDQ • Interface : SSTL_2 I/O compatible Standard 144-ball FBGA package • Pb-free package is availiable • Ordering Information Part Number EM6A9320BI-4M EM6A9320BI-4MG EM6A9320BI-5M EM6A9320BI-5MG EM6A9320BI-6M EM6A9320BI-6MG G : indicates Pb Free package. 4Mx32 DDR SDRAM Overview The EM6A9320 DDR SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits ...
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... G11 VDD K6 VDDQ J10 G2 VDD K7 VSS D4 A11 VDD K10 VSS D6 M3 VDDQ B2 VSS D7 L4 VDDQ B4 VSS D9 3 EM6A9320BI DQ29 DQ28 VSSQ DM3 DQ30 VDDQ VDDQ NC VSSQ VSSQ VSSQ DQ26 VSSQ VDDQ VSS VDD VSS VSSQ VDDQ DQ15 VSSQ VDDQ ...
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... DQ0 │ DQ31 4Mx32 DDR SDRAM CONTROL SIGNAL GENERATOR MODE REGISTER DQ BUFFER DM0~3 4 EM6A9320BI Column Decoder 4096 X 256 X 32 CELL ARRAY (BANK #0) Sense Amplifier Sense Amplifier 4096 X 256 X 32 CELL ARRAY (BANK #1) Column Decoder Column Decoder 4096 X 256 X 32 CELL ARRAY ...
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... Data I/O: The DQ0-DQ31 input and output data are synchronized with the positive Output edges of CK and CK#. The I/Os are byte-maskable during Writes. V Supply Power Supply: Power for the input buffers and core logic DD 4Mx32 DDR SDRAM Table 1. Pin Details of EM6A9320 Description 5 EM6A9320BI . Rev 0.9C May 2006 ...
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... ( ( EM6A9320BI . DDQ V Row Address Column Address A0~ code ...
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... EM6A9320BI Burst Lenght A3 Type 0 Sequential 1 Interleave Burst Length 0 ...
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... Issue MRS – with A8 to low to initialize the mode register. 4Mx32 DDR SDRAM DS1 Strength Full 100% 60% RFU RFU Do not use 30% Output driver matches impedance DDQ, 8 EM6A9320BI RFU must be set to “0” Comment V and V when all input signals are held TT REF Rev 0. DS0 DLL A0 ...
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... Rating Leaded - 0 -0.3 ~ 3.6 - 55~150 240 Min. Typ. 2.375 2.5 2.375 2 DDQ V – 0. REF REF V + 0.15 - REF Vssq - 0 0. EM6A9320BI Unit Pb-Free +0.3 V DDQ V 0~70 ° C ° C 260 ° Max. Unit Note 2.625 V 2.625 V V DDQ + 0.04 V REF V + 0.3 V DDQ V - 0.15 V REF - -15 ...
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... (min); IDD2P CK CK IDD2N IDD3P IDD3N IDD4 IDD5 IDD6 =t (min IDD7 =t (min (min and EM6A9320BI Unit Max 220 210 200 mA 260 240 240 100 100 100 230 220 220 mA 440 ...
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... DDR SDRAM and V 0.1+0. and V 0.1+0.01 DDQ SSQ Min V +0.4 REF - 0.8 0.5xV DDQ ) RFE See Figure. A Test Load V REF DDQ 50 Ω 30pF V =0 REF DDQ 11 EM6A9320BI Value Unit uF uF Max Unit - V V -0.4 V REF V +0.6 V DDQ -0.2 0.5xV +0.2 V DDQ 0 DDQ 1.5V +0 -0.4 V REF 1 V/ns V REF ...
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... 0.45 0.55 0.45 0.55 -0.7 0.7 -0.7 0.7 - 0.4 0.9 1.1 0.4 0.6 0.85 1. 0.35 - 0.4 0.6 0.4 0.6 0.4 0.6 0.9 - 0.9 - 0.45 - 0.45 - tCLMIN or tCLMIN or - tCHMIN - 0. tHP - tHP - QHS 100K 200 - tIS + 2tCK - tIS + 2tCK - 7.8 - 100 - 700 12 EM6A9320BI 5 6 Min Max Min 0.45 0.55 0.45 0.45 0.55 0.45 -0.7 0.7 -0.7 -0.7 0.7 -0.7 - 0.4 - 0.9 1.1 0.9 0.4 0.6 0.4 0.8 1.2 0. 0.25 - 0.25 0.4 0.6 0.4 0.4 0.6 0.4 0.4 0.6 0.4 1.0 - 1.0 1.0 - 1.0 0.5 - 0.5 0.5 - 0.5 tCLMIN or - tCHMIN tCHMIN - 0 tHP - QHS QHS ...
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... DQ0 DQ1 DQ2 DQ3 “Preamble” DQ0 DQ1 DQ2 DQ3 Valid “Postmble” t “Preamble” WPST t DQSS EM6A9320BI “Postmble” t DQSCK t RPST t AC QHS DQ0 DQ1 DQ2 DQ3 t QH “Postmble” “Postmble” “Postmble” ...
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... ACT Percharge Burst Stop for CAS Latency = DQ0 DQ1 Bank can be Active after Auto Precharge RDA CAS Latency = 3 Valid Begin of Auto Precharge 14 EM6A9320BI t RCDWR t t RAS PRE CMD ...
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... E it 4Mx32 DDR SDRAM Bank can be Active after Auto Precharge t WR Begin of Auto Precharge DQ2 DQ3 Db0 Da0 Da1 Db0 Db1 Db2 Db3 Da1 RFC CMD 15 EM6A9320BI 5 6 ACT Valid Db1 Db2 Db3 Rev 0.9C 8 May 2006 ...
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... EMRS MRS EMRS set MRS set Reset DLL with A8=H t MRD After 1 x CK, Command can be active NOP CMD t PDEX Power Down Mode Exit 16 EM6A9320BI RFC PREA AREF AREF Precharge All 2 or more MRS set Auto Refresh with A8=L Rev 0.9C MRS May 2006 ...
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... TOP VIEW PIN A1 CORNER SEATING PLANE 4Mx32 DDR SDRAM 1. 0.15 (4x) C Ball pitch : 0.80 Ball Diam eter : 0.45 0. EM6A9320BI BOTTOM VIEW PIN A1 CORNER 0. 0. 0.40~0.50 (144X) L 0.80 8.80 Rev 0.9C May 2006 ...