EM638325TS-7 Etron Technology, Inc., EM638325TS-7 Datasheet
EM638325TS-7
Available stocks
Related parts for EM638325TS-7
EM638325TS-7 Summary of contents
Page 1
... FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice Synchronous DRAM (SDRAM) Ordering Information Part Number EM638325TS-3.5 EM638325TS-4 EM638325TS-5 EM638325TS-5.5 EM638325TS-6 EM638325TS-7 EM638325TS-8 Part Number EM638325VF-3.5 EM638325VF-4 EM638325VF-5 EM638325VF-5.5 EM638325VF-6 EM638325VF-7 EM638325VF-8 ...
Page 2
EtronTech Overview The EM638325 SDRAM is a high-speed CMOS synchronous DRAM containing 64 Mbits internally configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock ...
Page 3
EtronTech Pin Descriptions Symbol Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. ...
Page 4
EtronTech Connect: These pins should be left unconnected. V Supply DQ Power: Provide isolated power to DQs for improved noise immunity. DDQ V Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity. SSQ V ...
Page 5
EtronTech Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Command State BankActivate (3) Idle BankPrecharge Any PrechargeAll Any Write (3) Active ...
Page 6
EtronTech Commands 1 BankActivate (RAS# = "L", CAS# = "H", WE# = "H" Bank, A0-A10 = Row Address) The BankActivate command activates the idle bank designated by the BS0,1 (Bank Select) signal. By latching the row address on ...
Page 7
EtronTech CLK COMMAND READ A NOP CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's Burst Read Operation(Burst Length = 4, CAS# Latency = 2, 3) The read data appears on the DQs subject ...
Page 8
EtronTech CLK DQM COMMAND NOP READ A DQ's : "H" or "L" Read to Write Interval (Burst Length CLK DQM COMMAND NOP NOP CAS# latency=2 t CK2 , DQ's : "H" or "L" Read ...
Page 9
EtronTech CLK Bank, ADDRESS Col A READ A COMMAND NOP CAS# latency=2 t CK2 , DQ's CAS# latency=3 t CK3 , DQ's 5 Read and AutoPrecharge command (RAS# = "H", CAS# = "L", WE# = "H", BS ...
Page 10
EtronTech CLK COM MAND NOP WRITE A 1 Clk Interval DIN A 0 DQ's Write Interrupted by a Write (Burst Length = 4, CAS# Latency = The Read command that interrupts a write burst ...
Page 11
EtronTech 7 Write and AutoPrecharge command (refer to the following figure) (RAS# = "H", CAS# = "L", WE# = "L" Bank, A10 = "H", A0-A7 = Column Address) The Write and AutoPrecharge command performs the precharge operation automatically ...
Page 12
EtronTech CLK t CK2 CKE CS# RAS# CAS# WE# ADDR. DQM Hi-Z DQ PrechargeAll The mode register is divided into various fields depending on functionality. Address BS0,1 A10/AP Function RFU* RFU* *Note: RFU (Reserved for future use) ...
Page 13
EtronTech Burst Type Field (A3) The Burst Type can be one of two modes, Interleave Mode or Sequential Mode. A3 Burst Type 0 Sequential 1 Interleave --- Addressing Sequence of Sequential Mode An internal column address is performed by increasing ...
Page 14
EtronTech Test Mode field (A8~A7) These two bits are used to enter the test mode and must be programmed to "00" in normal operation Write Burst Length (A9) This bit is used to select the ...
Page 15
EtronTech 11 Device Deselect command (CS# = "H") The Device Deselect command disables the command decoder so that the RAS#, CAS#, WE# and Address inputs are ignored, regardless of whether the CLK is enabled. This command is similar to the ...
Page 16
EtronTech Absolute Maximum Rating Symbol Input, Output Voltage IN OUT Power Supply Voltage DD DDQ T Operating Temperature OPR T Storage Temperature STG T Soldering Temperature (10s) SOLDER P Power Dissipation D I Short ...
Page 17
EtronTech Recommended D.C. Operating Conditions (V Description/Test condition Operating Current t t (min), Outputs Open, Input RC RC signal one transition per one cycle Precharge Standby Current in power down mode t = 15ns, CKE V (max Precharge ...
Page 18
EtronTech Electrical Characteristics and Recommended A.C. Operating Conditions (V = 3.3V 0.3V 0~70°C) (Note Symbol A.C. Parameter t Row cycle time RC (same bank) t Row activate to row activate delay RRD (different ...
Page 19
EtronTech LVTTL Interface Reference Level of Output Signals Output Load Input Signal Levels Transition Time (Rise and Fall) of Input Signals Reference Level of Input Signals Output 30pF LVTTL D.C. Test Load (A) 7. Transition times are measured between V ...
Page 20
EtronTech Timing Waveforms Figure 1. AC Parameters for Write Timing (Burst Length=4, CAS# Latency= CLK CK2 CKE CS# RAS# CAS# WE# BS0,1 t ...
Page 21
EtronTech Figure 2. AC Parameters for Read Timing (Burst Length=2, CAS# Latency= CLK CK2 CL CH CKE CS# RAS# CAS# WE# BS0,1 t A10 RAx t IS A0-A11 RAx ...
Page 22
EtronTech Figure 3. Auto Refresh (CBR) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 A0- DQM DQ PrechargeAll AutoRefresh Command Command Preliminary 2Mega x 32 SDRAM ...
Page 23
EtronTech Figure 4. Power on Sequene and Auto Refresh (CBR CLK t CK2 CKE High level is reauired CS# RAS# CAS# WE# BS0,1 A10 Address Key A0-A9 DQM Hi-Z PrechargeALL ...
Page 24
EtronTech Figure 5. Self Refresh Entry & Exit Cycle CLK *Note 2 *Note 1 CKE t IS CS# RAS# *Note 8 CAS# BS0,1 A0-A9 WE# DQM Hi-Z DQ Self Refresh Enter Note: To Enter SelfRefresh ...
Page 25
EtronTech Figure 6.1. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 RAx A10 A0-A9 RAx CAx DQM DQ Hi-Z Ax0 Ax1 ...
Page 26
EtronTech Figure 6.2. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 CAx RAx DQM Hi-Z DQ Ax0 Activate ...
Page 27
EtronTech Figure 6.3. Clock Suspension During Burst Read (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 CAx RAx DQM Hi-Z DQ Activate ...
Page 28
EtronTech Figure 7.1. Clock Suspension During Burst Write (Using CKE) (Burst Length = 4, CAS# Latency = CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM ...
Page 29
EtronTech Figure 7.2. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAx A0-A9 RAx CAx DQM Hi-Z DQ DAx0 DAx1 ...
Page 30
EtronTech Figure 7.3. Clock Suspension During Burst Write (Using CKE) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0-A9 RAx CAx DQM DQ Hi-Z DAx0 Activate ...
Page 31
EtronTech Figure 8. Power Down Mode and Clock Mask (Burst Lenght=4, CAS# Latency= CLK t CK2 t IS CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx A0~A9 DQM Hi-Z DQ ACTIVE STANDBY Activate ...
Page 32
EtronTech Figure 9.1. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw RAw CAw A0~A9 DQM Hi-Z DQ Aw0 Aw1 Aw2 ...
Page 33
EtronTech Figure 9.2. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BA0,1 A10 RAw CAw RAw A0~A9 DQM Hi-Z DQ Aw0 Activate Read ...
Page 34
EtronTech Figure 9.3. Random Column Read (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAw A0~A9 CAw RAw DQM Hi-Z DQ Activate Read Command ...
Page 35
EtronTech Figure 10.1. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RBw CBw A0~A9 RBw DQM Hi-Z DQ DBw0DBw1DBw2 DBw3 DBx0 ...
Page 36
EtronTech Figure 10.2. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 RBw A10 A0~A9 RBw CBw DQM Hi-Z DQ DBw0 DBw1 D ...
Page 37
EtronTech Figure 10.3. Random Column Write (Page within same Bank) (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RBw A10 A0~A9 RBw CBw DQM Hi-Z DBw0 DBw1DBw2 DBw3 DBx0 ...
Page 38
EtronTech Figure 11.1. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS# CAS# WE# BS0,1 RBx A10 RBx CBx A0~A9 t RCD t DQM AC1 Hi-Z ...
Page 39
EtronTech Figure 11.2. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RBx A10 A0~A9 RBx CBx t t RCD AC2 DQM Hi-Z Bx0 ...
Page 40
EtronTech Figure 11.3. Random Row Read (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RBx RBx A0~A9 CBx t t RCD AC3 DQM Hi-Z DQ ...
Page 41
EtronTech Figure 12.1. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK1 CKE High CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 ...
Page 42
EtronTech Figure 12.2. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx A0~A9 RAx CAx t RCD DQM Hi-Z DQ DAx0 DAx1 ...
Page 43
EtronTech Figure 12.3. Random Row Write (Interleaving Banks) (Burst Length=8, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx A0~A9 t RCD DQM Hi-Z DQ DAx0DAx1 DAx2 ...
Page 44
EtronTech Figure 13.1. Read and Write Cycle (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx A0~A9 DQM Hi-Z DQ Ax0 Ax1 Ax2 Activate Command Bank ...
Page 45
EtronTech Figure 13.2. Read and Write Cycle (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx A0~A9 DQM Hi-Z DQ Ax0 Activate Read Command Command ...
Page 46
EtronTech Figure 13.3. Read and Write Cycle (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx CAx RAx A0~A9 DQM Hi-Z DQ Read Activate Command Command Bank A ...
Page 47
EtronTech Figure 14.1. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw RAx RBw RAx A0~ AC1 RCD DQM Hi-Z DQ ...
Page 48
EtronTech Figure 14.2. Interleaving Column Read Cycle (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAy RAx RAx A0~ RCD AC2 DQM Hi-Z DQ ...
Page 49
EtronTech Figure 14.3. Interleaved Column Read Cycle (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RAx CAx RBx A0~ RCD DQM Hi-Z DQ Activate ...
Page 50
EtronTech Figure 15.1. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw RAx CAx RBw A0~A9 t RCD DQM t RRD Hi-Z DQ ...
Page 51
EtronTech Figure 15.2. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw RAx RBw CAx A0~A9 t RCD DQM t RRD Hi-Z DQ ...
Page 52
EtronTech Figure 15.3. Interleaved Column Write Cycle (Burst Length=4, CAS# Latency= CLK t CK3 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBw RAx CAx RBw A0~A9 t RCD DQM t > t RRD ...
Page 53
EtronTech Figure 16.1. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency= CLK t CK1 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RBx CBx RAx CAx RBx A0~A9 DQM Hi-Z DQ Ax1 ...
Page 54
EtronTech Figure 16.2. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RAx RBx CAx A0~A9 DQM Hi-Z DQ Ax1 Ax0 ...
Page 55
EtronTech Figure 16.3. Auto Precharge after Read Burst (Burst Length=4, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 CAx RAx RBx A0~A9 DQM Hi-Z DQ Activate Activate ...
Page 56
EtronTech Figure 17.1. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency= CLK t CK1 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RBx RAx CAx CBx A0~A9 DQM Hi-Z DQ DAx0 ...
Page 57
EtronTech Figure 17.2. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 CAx A0~A9 RAx RBx DQM Hi-Z DQ DAx0 DAx1 ...
Page 58
EtronTech Figure 17.3. Auto Precharge after Write Burst (Burst Length=4, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx A9 RAx RAx CAx RBx A0~A9 DQM Hi-Z DQ DAx0 DAx1 ...
Page 59
EtronTech Figure 18.1. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency= CLK t CK1 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RBx RBx A0~A9 RAx CAx t RRD DQM Hi-Z DQ ...
Page 60
EtronTech Figure 18.2. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RBx A10 RAx RAx CAx RBx A0~A9 DQM Hi Ax+1 ...
Page 61
EtronTech Figure 18.3. Full Page Read Cycle (Burst Length=Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A10 RAx CAx RBx A0~A9 DQM Hi-Z DQ Activate ...
Page 62
EtronTech Figure 19.1. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency= CLK t CK1 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A10 RAx CAx RBx A0~A9 DQM Hi-Z DQ DAx DAx+ ...
Page 63
EtronTech Figure 19.2. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx RBx A10 RAx CAx A0~A9 RBx DQM Hi-Z DQ DAx DAx+ ...
Page 64
EtronTech Figure 19.3. Full Page Write Cycle (Burst Length=Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RBx RAx A10 RAx CAx RBx A0~A9 DQM Hi-Z DQ DAx DAx+ ...
Page 65
EtronTech Figure 20. Byte Write Operation (Burst Length=4, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx A0~A9 CAx LDQM UDQM DQ0 - DQ7 Ax0 DQ8 - DQ15 ...
Page 66
EtronTech Figure 21. Random Row Read (Interleaving Banks) (Burst Length=2, CAS# Latency= CLK t CK1 High CKE Begin Auto Begin Auto Precharge Precharge Bank B Bank A CS# RAS# CAS# WE# BS0,1 RAu RBu ...
Page 67
EtronTech Figure 22. Full Page Random Column Read (Burst Length=Full Page, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAx RBx CAx CBx A0~A9 DQM t t RRD ...
Page 68
EtronTech Figure 23. Full Page Random Column Write (Burst Length=Full Page, CAS# Latency= CLK t CK2 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RBx RAx RBx CAx CBx A0~A9 DQM t t RRD ...
Page 69
EtronTech Figure 24.1. Precharge Termination of a Burst (Burst Length=Full Page, CAS# Latency= CLK t CK1 CKE CS# RAS# CAS# WE# BS0,1 A10 RAx RAx CAx A0~A9 DQM DQ DAx0 DAx1 DAx2 DAx3 ...
Page 70
EtronTech Figure 24.2. Precharge Termination of a Burst (Burst Length=8 or Full Page, CAS# Latency= CLK t CK2 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 RAx CAx A0~A9 DQM DQ DAx0 DAx1 ...
Page 71
EtronTech Figure 24.3. Precharge Termination of a Burst (Burst Length= Full Page, CAS# Latency= CLK t CK3 High CKE CS# RAS# CAS# WE# BS0,1 RAx A10 A0~A9 RAx CAx t WR DQM ...
Page 72
EtronTech 86 Pin TSOP II Package Outline Drawing Information Symbol Dimension in inch Min Normal A A1 0.002 0.004 A2 0.037 0.039 B 0.007 0.008 C 0.005 D 0.87 0.875 E 0.395 ...
Page 73
EtronTech Preliminary 2Mega x 32 SDRAM 73 Rev 0.8 EM638325 Nov 2001 ...