KM44C16104BS-6 Samsung, KM44C16104BS-6 Datasheet

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KM44C16104BS-6

Manufacturer Part Number
KM44C16104BS-6
Description
16M x 4-Bit CMOS Dynamic RAM with Extended Data Out
Manufacturer
Samsung
Datasheet

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KM44C16104BS-6
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KM44C16004B, KM44C16104B
FEATURES
• Part Identification
• Performance Range
This is a family of 16,777,216 x 4 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -5, or -6), package type (SOJ or
TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capa-
bilities. This 16Mx4 EDO Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low
power consumption and high reliability.
• Refresh Cycles
* Access mode & RAS only refresh mode
• Active Power Dissipation
KM44C16004B*
KM44C16104B
Speed
CAS-before-RAS & Hidden refresh mode
- KM44C16004B(5.0V, 8K Ref.)
- KM44C16104B(5.0V, 4K Ref.)
: 8K cycle/64ms
: 4K cycle/64ms
-45
-5
-6
Speed
-45
-5
-6
Part
NO.
45ns
50ns
60ns
t
RAC
Refresh
12ns
13ns
15ns
cycle
t
16M x 4bit CMOS Dynamic RAM with Extended Data Out
550
495
440
CAC
8K
8K
4K
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
104ns
74ns
84ns
t
RC
Refresh time
Normal
64ms
715
660
605
4K
Unit : mW
17ns
20ns
25ns
t
HPC
DESCRIPTION
(A0~A11)*1
(A0~A11)*1
A0~A12
A0~A10
RAS
CAS
W
FUNCTIONAL BLOCK DIAGRAM
• Extended Data Out Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Fast parallel test mode capability
• TTL(5.0V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +5.0V 10% power supply
Note) *1 : 4K Refresh
Control
Clocks
Row Address Buffer
Col. Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
VBB Generator
Column Decoder
16,777,216 x 4
Memory Array
Row Decoder
Cells
CMOS DRAM
Vcc
Vss
Data out
Data in
Buffer
Buffer
OE
DQ0
DQ3
to

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KM44C16104BS-6 Summary of contents

Page 1

... Refresh cycle(4K Ref Ref.), access time (-45, -5, or -6), package type (SOJ or TSOP-II) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capa- bilities. This 16Mx4 EDO Mode DRAM family is fabricated using Samsung s advanced CMOS process to realize high band-width, low power consumption and high reliability. ...

Page 2

KM44C16004B, KM44C16104B •KM44C160(1)04BK DQ0 2 DQ1 3 N.C 4 N.C 5 N RAS 400mil ...

Page 3

KM44C16004B, KM44C16104B ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Voltage on V supply relative Storage Temperature Power Dissipation Short Circuit Output Current * Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" ...

Page 4

KM44C16004B, KM44C16104B DC AND OPERATING CHARACTERISTICS Symbol Power I Don t care CC1 I Normal Don t care CC2 I Don t care CC3 I Don t care CC4 I Normal Don t care CC5 I Don t care CC6 ...

Page 5

KM44C16004B, KM44C16104B CAPACITANCE (T = Parameter Input capacitance [A0 ~ A12] Input capacitance [RAS, CAS, W, OE] Output capacitance [DQ0 - DQ3] AC CHARACTERISTICS ( Test condition : V =5.0V 10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.0/0.8V CC Parameter ...

Page 6

KM44C16004B, KM44C16104B AC CHARACTERISTICS (Continued) Parameter Data hold time Refresh period (4K, Normal) Refresh period (8K, Normal) Write command set-up time CAS to W delay time RAS to W delay time Column address to W delay time CAS set-up time ...

Page 7

KM44C16004B, KM44C16104B TEST MODE CYCLE Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address RAS pulse width CAS pulse width RAS hold time CAS hold time ...

Page 8

KM44C16004B, KM44C16104B NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved (min) and V (max) are reference levels for measuring ...

Page 9

KM44C16004B, KM44C16104B READ CYCLE RAS CAS ASR ADDRESS ...

Page 10

KM44C16004B, KM44C16104B WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ADDRESS ...

Page 11

KM44C16004B, KM44C16104B WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR ADDRESS V - ...

Page 12

KM44C16004B, KM44C16104B READ - MODIFY - WRITE CYCLE RAS CRP CAS ASR ROW A ADDR ...

Page 13

KM44C16004B, KM44C16104B HYPER PAGE READ CYCLE RAS CRP CAS ASR RAH ROW A ADDR ...

Page 14

KM44C16004B, KM44C16104B HYPER PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : D = OPEN OUT RAS CRP CAS ASR RAH ROW ...

Page 15

KM44C16004B, KM44C16104B HYPER PAGE READ-MODIFY-WRITE CYCLE RAS CRP CAS RAD t ASR t ASC ROW A ADDR ...

Page 16

KM44C16004B, KM44C16104B HYPER PAGE READ AND WRITE MIXED CYCLE RAS CAS t RAD RAH t ASR ROW A ADDR ...

Page 17

KM44C16004B, KM44C16104B RAS - ONLY REFRESH CYCLE* NOTE : W, OE Don t care OPEN OUT RAS CRP CAS ASR ...

Page 18

KM44C16004B, KM44C16104B HIDDEN REFRESH CYCLE ( READ ) RAS CRP CAS ASR ADDRESS ...

Page 19

KM44C16004B, KM44C16104B HIDDEN REFRESH CYCLE ( WRITE ) NOTE : D = OPEN OUT RAS CAS ASR ADDRESS ...

Page 20

KM44C16004B, KM44C16104B CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE Don t care RAS CAS DQ0 ~ DQ3(7) t CEZ V - ...

Page 21

KM44C16004B, KM44C16104B PACKAGE DIMENSION 32 SOJ 400mil #32 #1 0.0375 (0.95) 0.050 (1.27) 32 TSOP(II) 400mil 0.037 (0.95) 0.050 (1.27) 0.841 (21.36) MAX 0.820 (20.84) 0.830 (21.08) 0.026 (0.66) 0.032 (0.81) 0.015 (0.38) 0.021 (0.53) 0.841 (21.35) MAX 0.821 (20.85) ...

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