MB81V18165B-60PFTN Fujitsu, MB81V18165B-60PFTN Datasheet
MB81V18165B-60PFTN
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MB81V18165B-60PFTN Summary of contents
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... Since the standby current of the MB81V18165B is very small, the device can be used as a non- volatile memory in equipment that uses batteries for primary and/or auxiliary power. ...
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... MB81V18165B-50/-60/-50L/-60L PACKAGE 42-pin plastic SOJ (LCC-42P-M01) Package and Ordering Information – 42-pin plastic (400 mil) SOJ, order as MB81V18165B- – 50-pin plastic (400 mil) TSOP (II) with normal bend leads, order as MB81V18165B- and MB81V18165B- LPFTN (Low Power) 2 50-pin plastic TSOP (II) (FPT-50P-M06) ...
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... N. N. RAS MB81V18165B-50/-60/-50L/-60L V Designator RAS LCAS DQ 9 N.C. UCAS LCAS WE UCAS ...
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... MB81V18165B-50/-60/-50L/-60L Fig. 1 – MB81V18165B DYNAMIC RAM - BLOCK DIAGRAM RAS UCAS LCAS Mode Control Address A 4 Buffer & A Pre- 5 Decoder Refresh Address Counter 4 Clock Gen #1 Write Clock Clock Gen #2 Column Decoder Sense Amp & ...
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... UCAS and the setup/hold times are referenced to each LCAS and UCAS because WE goes Low before LCAS/UCAS delayed write or a read-modify-write cycle, WE goes Low after LCAS/UCAS; thus, input data is strobed by WE and all setup/hold times are referenced to the write-enable signal. MB81V18165B-50/-60/-50L/-60L Input/Output Data Address Input ...
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... For each page of memory (within column address locations), any of 1,024 16 bits can be accessed and, when multiple MB81V18165Bs are used, CAS is decoded to select the desired memory page. Hyper page mode operations need not be addressed sequentially and combinations of read, write, and/or read-modify-write cycles are permitted ...
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... Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand. CAPACITANCE Parameter Input Capacitance Input Capacitance, RAS, LCAS, UCAS, WE, OE Input/Output Capacitance MB81V18165B-50/-60/-50L/-60L Symbol OUT ...
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... Power *2 MB81V18165B Supply Current) -60/60L MB81V18165B -50/50L Hyper Page Mode *2 Current MB81V18165B -60/60L MB81V18165B Refresh Current#2 -50/50L (Average Power *2 MB81V18165B Supply Current) -60/60L MB81V18165B -50/60 Battery Backup Current *2 (Average Power Supply Current) MB81V18165B -50L/60L Refresh Current#3 MB81V18165B (Average Power -50L/60L Supply Current) ...
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... CPN t 0 ASR t 7 RAH t 0 ASC t 7 CAH * RAD t 25 RAL t 18 CAL t 0 RCS MB81V18165B -60/60L Unit Max. Min. Max. 16.4 — 16.4 ms 128 — 128 — 104 — ns — 138 — — — — ...
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... CDD * — DZC * — DZO t 5 — OEP t 7 — OECH t 5 — WPZ t 13 — WED MB81V18165B -60/60L Unit Min. Max. 0 — — — — — — — — — ...
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... MB81V18165B-50/-60/-50L/-60L MB81V18165B -50/50L Notes Symbol Min. t — 100000 RASP t 20 HPC t 59 HPRWC *9,18 t — CPA RHCP * CPWD MB81V18165B -60/60L Unit Max. Min. Max. — 100000 ns — 25 — ns — 69 — — — 10 — ns — 35 — ns — ...
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... MB81V18165B-50/-60/-50L/-60L Notes: *1. Referenced *2. I depends on the output load conditions and cycle rates; the specified values are obtained with the CC output open. I depends on the number of address change as RAS = and I CC1 CC3 CC4 V , LCAS = CC2 all address signals are fixed steady state ...
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... Fig. 2 – t vs. t RAC RCD t (ns) RAC version version (ns) RCD MB81V18165B-50/-60/-50L/-60L Fig. 3 – t vs. t RAC RAD t (ns) RAC version version (ns) RAD Fig. 4 – ...
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... MB81V18165B-50/-60/-50L/-60L V IH RAS CRP LCAS UCAS t ASR V IH ROW ADDRESS (Output (Input DESCRIPTION To implement a read operation, a valid address is latched by the RAS and LCAS or UCAS address strobes and with WE set to a High level and OE set to a Low level, the output is valid once the memory access time has elapsed ...
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... During all write cycles, timing parameters and t must be satisfied. In the early write cycle shown above t RWL CWL RAL CAL the falling edge of LCAS or UCAS and written into memory. MB81V18165B-50/-60/-50L/-60L Fig. 6 – EARLY WRITE CYCLE RAS t CSH t t RCD ...
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... MB81V18165B-50/-60/-50L/-60L Fig. 7 – DELAYED WRITE CYCLE (OE CONTROL RAS CRP LCAS UCAS t t ASR RAH V IH ROW ADD (Input (Output DESCRIPTION In the delayed write cycle not satisfied ...
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... DESCRIPTION The read-modify-write cycle is executed by changing WE from High to Low after the data appears on the DQ pins. In the read- modify-write cycle, OE must be changed from Low to High after the memory access time. MB81V18165B-50/-60/-50L/-60L t RWC t RAS t AR RCD t ASC t ...
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... MB81V18165B-50/-60/-50L/-60L V IH RAS RAD t CRP LCAS UCAS t ASR t RAH V IH ROW ADD RCS DZC (Input HIGH-Z (Output During one cycle is achieved, the input/output timing apply the same manner as the former cycle. ...
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... This operation is performed by strobing in the row address and maintaining RAS at a Low level and High level during all successive memory cycles in which the row address is latched. The address time is determined by t one is the latest in occurring. MB81V18165B-50/-60/-50L/-60L t RASP t ...
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... MB81V18165B-50/-60/-50L/-60L Fig. 11 – HYPER PAGE MODE READ CYCLE (WE CONTROL RAS CRP LCAS RAD UCAS t ASR t RAH V ROW ADD RCS DZC (Input HIGH-Z (Output ...
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... WE and OE are reversed. Data appearing on the latched on the falling edge of UCAS and the data is written into the memory. During the hyper page mode early 9 16 write cycle, including the delayed (OE) write and read-modify-write cycles, t MB81V18165B-50/-60/-50L/-60L t RASP t HPC t t ...
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... MB81V18165B-50/-60/-50L/-60L Fig. 13 – HYPER PAGE MODE DELAYED WRITE CYCLE V IH RAS CRP LCAS UCAS t ASR V ROW ADDRESS (Input (Output DESCRIPTION The hyper page mode delayed write cycle is executed in the same manner as the hyper page mode early write cycle except for the states of WE and OE ...
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... (Input HIGH-Z (Output DZO DESCRIPTION The hyper page mode performs read/write operations repetitively during one RAS cycle. At this time, t MB81V18165B-50/-60/-50L/-60L t RASP t HPC t t CSH CP t CAS t CAS t ASR t CAL t CAL t t CAH CAH ...
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... MB81V18165B-50/-60/-50L/-60L Fig. 15 – HYPER PAGE MODE READ-MODIFY-WRITE CYCLE V IH RAS CRP LCAS UCAS t ASR V IH ROW ADDRESS (Input HIGH-Z (Output DESCRIPTION During the hyper page mode of operation, the read-modify-write cycle can be executed by switching WE from High to Low after input data appears at the DQ pins during a normal cycle ...
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... CAS-before-RAS refresh is an on-chip refresh capability that eliminates the need for external refresh addresses. If LCAS or UCAS is held Low for the specified setup time (t CSR address counter are enabled. An internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next CAS-before-RAS refresh operation. MB81V18165B-50/-60/-50L/-60L t t RAS t ...
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... MB81V18165B-50/-60/-50L/-60L V IH RAS V IL LCAS UCAS t ASR V IH ROW ADDRESS (Input (Output DESCRIPTION A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of LCAS or UCAS and cycling RAS ...
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... Read and check data written in procedure 4) by using normal read cycle for all 1,024 memory locations. 6) Reverse test data and repeat procedures 3), 4), and 5). No. Parameter 69 Access Time for CAS 70 Column Address Hold Time 71 CAS to WE Delay Time 72 CAS Pulse Width 73 RAS Hold Time MB81V18165B-50/-60/-50L/-60L t t FRSH CP t FCAS t FCAH t ASC COLUMN ADDRESSES t t ...
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... RASS < Read/Write operation can be performed non refresh time within t t RPS t RPC t CHS HIGH-Z “L” or “L” “H” transition (Address and DQ) MB81V18165B-60L Max. Min. Max. — 100 — — 104 — — –50 — Note: Assumes Self Refresh cycle only. ...
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... INDEX 1.27±0.13 LEAD No 1 (.050±.005) 25.40(1.000)REF "A" 0.10(.004) 1995 FUJITSU LIMITED C42001S-2C-1 C MB81V18165B-50/-60/-50L/-60L Resin protrusion. (Each side: 0.15 (.006) MAX) 22 10.16 (.400) 10.97±0.13 (.432±.005) NOM 21 2.50(.098)NOM +0.35 +.014 3.40 .134 −0.20 −.008 2 ...
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... MB81V18165B-50/-60/-50L/-60L (Continued) 50-pin plastic TSOP(II) (FPT-50P-M06 INDEX "A" LEAD No 20.95±0.10(.825±.004) 0.30±0.10 (.012±.004) 0.80(.031)TYP 1994 FUJITSU LIMITED F50006S-2C 0.05(.002)MIN (STAND OFF) 1.15±0.05(.045±.002) 0.13(.005) M 0.10(.004) 19.20(.756)REF Resin protrusion. (Each side: 0.15 (.006) MAX) Details of " ...
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... Tel: (65) 281-0770 Fax: (65) 281-0220 http://www.fmap.com.sg/ F9709 FUJITSU LIMITED Printed in Japan MB81V18165B-50/-60/-50L/-60L All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use ...