QG82945GM Intel Corporation, QG82945GM Datasheet
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Intel E7501 Chipset Memory Controller Hub (MCH) Datasheet July 2003 Document Number: 251927-002 ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. ® ® Intel, Intel Xeon, Intel Pentium M Processor and the Intel logo are trademarks or registered trademarks of Intel corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2002, Intel Corporation 2 ® ...
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Contents 1 Introduction ................................................................................................................ 13 1.1 Terminology......................................................................................................... 13 1.2 Reference Documents......................................................................................... 14 ® 1.3 Intel E7501 Chipset System Architecture.......................................................... 15 2 Signal Description 2.1 System Bus Interface Signals ............................................................................. 19 2.2 DDR Channel A Signals ...................................................................................... 22 2.3 DDR Channel ...
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DRT—DRAM Timing Register (D0:F0) .................................................. 48 3.5.21 DRC—DRAM Controller Mode Register (D0:F0) ................................... 50 3.5.22 CKDIS—CK / CK# Disable Register (D0:F0) ......................................... 51 3.5.23 CFGCTL—Configuration Control Register (D0:F0)................................ 52 3.5.24 SMRAMC—System Management RAM Control Register (D0:F0)......... 53 3.5.25 ESMRAMC—Extended ...
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DID—Device Identification Register (D2:F0) .......................................... 81 3.7.3 PCICMD—PCI Command Register (D2:F0) .......................................... 82 3.7.4 PCISTS—PCI Status Register (D2:F0) .................................................. 83 3.7.5 RID—Revision Identification Register (D2:F0) ....................................... 84 3.7.6 SUBC—Sub-Class Code Register (D2:F0) ............................................ 84 3.7.7 BCC—Base Class Code Register ...
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Device 3 Memory and Prefetchable Memory ....................................... 114 4.1.10 Device 4 Memory and Prefetchable Memory ....................................... 114 4.1.11 HI_A Subtractive Decode ..................................................................... 114 4.2 I/O Address Space ............................................................................................ 114 4.3 SMM Space....................................................................................................... 115 4.3.1 System Management Mode (SMM) Memory ...
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Hub Interface 2.0 DC Characteristics ................................................... 135 6.4.6 Hub Interface 1.5 DC Characteristics ................................................... 136 6.4.7 SMBus DC Characteristics ................................................................... 137 6.4.8 Reset and Miscellaneous CMOS Inputs DC Characteristics................ 137 7 Ballout and Package Specifications 7.1 Ballout ............................................................................................................... 139 ...
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Figures ® 1-1 Intel E7501 Chipset MCH Platform Block Diagram........................................... 16 2-1 MCH Interface Signals ........................................................................................ 18 3-1 PAM Registers .................................................................................................... 45 4-1 System Address Map ........................................................................................ 109 4-2 Detailed Extended Memory Range Address Map ............................................. 110 ® 5-1 Intel ...
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Operating Condition Supply Voltage ................................................................. 132 6-10 System Bus Interface DC Characteristics .........................................................133 6-11 DDR Interface DC Characteristics.....................................................................134 6-12 Hub Interface 2.0 DC Characteristics ................................................................135 6-13 Hub Interface 1.5 DC Characteristics ................................................................136 6-14 SMBus DC Characteristics................................................................................ 137 6-15 Reset ...
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Revision History Revision -002 Added support for Intel New definition added to the DRT - DRAM Timing Register Bits 18:16, 001 = 0 clocks Table 6-2, “DC Characteristics Functional Operating Range“ with new parameters for the Intel Table 6-9, “Operating ...
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Intel E7501 Chipset MCH Features ■ Processor/Host Bus Support ® — Intel Xeon™ processor with 512-KByte L2 cache, Intel processor with 533 MHz system bus and ® Intel Pentium 1 Mbyte of L2 cache — 400 MHz or 533 ...
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This page is intentionally left blank. ® Intel E7501 Chipset MCH Datasheet ...
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Introduction ® The Intel E7501 chipset is targeted for the server market, both front-end and general-purpose, low- to mid-range intended to be used with the Intel ® cache and the Intel for the applied-computing market intended ...
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Introduction Term Single Bank DIMM Double Bank DIMM ® Intel x4 Single Device Data Correction (X4 SDDC) RASUM 1.2 Reference Documents For the server market, refer to the Intel Compatible Platform Design Guide and your Field Representative for an expanded ...
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Intel E7501 Chipset System Architecture The E7501 chipset is optimized for the Intel Intel Xeon processor with 533 MHz system bus, and the Intel architecture of the chipset provides the performance and feature set required for dual-processor– based ...
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Introduction ® Figure 1-1. Intel E7501 Chipset MCH Platform Block Diagram SMBus Devices GPIOs LPC I/F Super I/O 1–4 FWHs 10/100 LAN Controller AC'97 2.1 AC '97 Codec(s) USB 1.1, 6 Ports 4 IDE Devices UltraATA/100 16 Processor Processor MCH ...
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Signal Description This chapter provides a detailed description of the E7501 chipset MCH signals. The signals are arranged in functional groups according to their associated interface. The “#” symbol at the end of a signal name indicates that the active, ...
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Signal Description Figure 2-1. MCH Interface Signals HDSTBP[3:0]#/HDSTBN[3:0]# HCLKINP, HLCKINN HXSWNG, HYSWNG HXRCOMP, HYRCOMP CMDCLK_A[3:0], CMDCLK_A[3:0]# CMDCLK_B[3:0], CMDCLK_B[3:0]# NOTE: Channel B is not active in single-channel mode. 18 HA[35:3]# HD[63:0]# ADS# BNR# BPRI# DBSY# DEFER# DRDY# HIT# HITM# HLOCK# HREQ[4:0]# ...
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System Bus Interface Signals Table 2-1. Signal Description (Sheet Signal Name Type ADS# AGTL+ AP[1:0]# AGTL+ XERR# AGTL+ BINIT# AGTL+ BNR# AGTL+ BPRI# AGTL+ BREQ0# AGTL+ CPURST# AGTL+ DBI[3:0]# AGTL+ DBSY# AGTL+ DEFER# AGTL+ DP[3:0]# AGTL+ ...
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Signal Description Table 2-1. Signal Description (Sheet Signal Name Type HA[35:3]# AGTL+ HADSTB[1:0]# AGTL+ HD[63:0]# AGTL+ HDSTBP[3:0]# AGTL+ HDSTBN[3:0]# HIT# AGTL+ HITM# AGTL+ HLOCK# AGTL+ HREQ[4:0]# AGTL+ HTRDY# AGTL+ RS[2:0]# AGTL+ 20 I/O Host Address Bus: HA[35:3]# ...
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Table 2-1. Signal Description (Sheet Signal Name Type RSP# AGTL+ HCLKINP HCLKINN Analog HDVREF[3:0] Analog HAVREF[1:0] Analog HCCVREF Analog HXSWNG HYSWNG Analog HXRCOMP HYRCOMP Analog ® Intel E7501 Chipset MCH Datasheet Response Parity: RSP# provides parity protection ...
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Signal Description 2.2 DDR Channel A Signals Table 2-2. DDR Channel_A Channel Signals Signal Name CB_A[7:0] DQ_A[63:0] DQS_A[17:0] CMDCLK_A[3:0], CMDCLK_A[3:0]# MA_A[12:0] BA_A[1:0] RAS_A# CAS_A# WE_A# CS_A[7:0]# CKE_A RCVEN_A DDRCOMP_A DDRCVO_A DDRVREF_A[3:0] ODTCOMP 22 Type I/O DDR Channel A Check Bits: ...
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DDR Channel B Signals Table 2-3. DDR Channel_B Channel Signals Signal Name CB_B[7:0] DQ_B[63:0] DQS_B[17:0] CMDCLK_B[3:0], CMDCLK_B[3:0]# MA_B[12:0] BA_B[1:0] RAS_B# CAS_B# WE_B# CS_B[7:0]# CKE_B RCVEN_B DDRCOMP_B DDRCVO_B DDRVREF_B[3:0] NOTE: Channel B is not active in single-channel mode. ® Intel ...
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Signal Description 2.4 Hub Interface_A Signals Table 2- Signals Signal Name HI_A[11:0] HI_STBF HI_STBS HIRCOMP_A HISWNG_A HIVREF_A 24 Type I/O HI_A Signals: These signals are used for the hub interface between the (as/t/s) ® Intel ICH3-S and the ...
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Hub Interface_B Signals 1) Table 2-5. HI_B Signals Signal Name HI_B[21:20] HI_B[18:0] PSTRBF_B PSTRBS_B PUSTRBF_B PUSTRBS_B HIRCOMP_B HISWNG_B HIVREF_B ® Intel E7501 Chipset MCH Datasheet Type I/O HI_B Signals: These are the ECC signals used for connection between the ...
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Signal Description 2.6 Hub Interface_C Signals Table 2-6. HI_C Signals Signal Name HI_C[21:20] (as/t/s) CMOS HI_C[18:0] (as/t/s) CMOS PSTRBF_C (as/t/s) CMOS PSTRBS_C (as/t/s) CMOS PUSTRBF_C (as/t/s) CMOS PUSTRBS_C (as/t/s) CMOS HIRCOMP_C CMOS HISWNG_C Analog HIVREF_C Analog 26 Type I/O HI_C ...
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Hub Interface_D Signals Table 2-7. HI_D Signals Signal Name HI_D[21:20] (as/t/s) CMOS HI_D[18:0] (as/t/s) CMOS PSTRBF_D (as/t/s) CMOS PSTRBS_D (as/t/s) CMOS PUSTRF_D (as/t/s) CMOS PUSTRS_D (as/t/s) CMOS HIRCOMP_D CMOS HISWNG_D Analog HIVREF_D Analog ® Intel E7501 Chipset MCH Datasheet ...
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Signal Description 2.8 Clocks, Reset, Power, and Miscellaneous Signals Table 2-8. Clocks, Reset, Power, and Miscellaneous Signals Signal Name CLK66 RSTIN# XORMODE# PWRGOOD SMB_CLK SMB_DATA VCC1_2 VCCA1_2 VCCAHI1_2 VCCACPU1_2 VCC_CPU VCC2_5 VSS 28 Type 66 MHz Clock In: This pin ...
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Register Description The MCH contains two sets of software accessible registers, accessed via the host processor I/O address space: • Control registers – These registers are I/O mapped into the processor I/O space, which control access to PCI configuration space ...
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Register Description Term Default Value Upon a Full Reset, the MCH sets all of its internal configuration registers to predetermined upon a Reset default states. Some register values at reset are determined by external strapping options. The default state represents ...
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Standard PCI Configuration Mechanism The PCI Bus defines a slot-based configuration space that allows each device to contain up to eight functions; each function contains up to 256, 8-bit configuration registers. The PCI specification defines two bus cycles to ...
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Register Description 3.3.1 Logical PCI Bus 0 Configuration Mechanism The MCH decodes the Bus Number (bits 23:16) and the Device Number (bits 15:11) fields of the CONFIG_ADDRESS register. When the Bus Number field of CONFIG_ADDRESS is 0, the configuration cycle ...
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I/O Mapped Registers The MCH contains two registers that reside in the processor I/O address space: the Configuration Address (CONFIG_ADDRESS) Register and the Configuration Data (CONFIG_DATA) Register. The Configuration Address Register enables/disables the configuration space and determines what portion ...
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Register Description 3.5 Chipset Host Controller Registers (Device 0, Function 0) The Chipset Host Controller registers are in Device 0 (D0), Function 0 (F0). register address map for this device, function. Warning: Address locations not listed in the table are ...
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VID—Vendor Identification Register (D0:F0) Address Offset: Default: Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identifies any PCI device. Default, Bits Access 8086h 15:0 RO 3.5.2 DID—Device ...
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Register Description 3.5.3 PCICMD—PCI Command Register (D0:F0) Address Offset: Default: Access: Size: Since MCH Device 0 does not physically reside on PCI_A, portions of this register are not implemented. Default, Bits Access 15:10 00h R/W ...
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PCISTS—PCI Status Register (D0:F0) Address Offset: Default: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI interface. Since MCH Device 0 does not physically reside on PCI_A, many of ...
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Register Description 3.5.5 RID—Revision Identification Register (D0:F0) Address Offset: Default: Access: Size: This register contains the revision number of the MCH Device 0. Default, Bits Access 01h 7:0 RO 3.5.6 SUBC—Sub-Class Code Register (D0:F0) Address Offset: Default: Access: Size: This ...
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MLT—Master Latency Timer Register (D0:F0) Address Offset: Default: Access: Size: Device 0 in the MCH is not a PCI master. Therefore, this register is not implemented. Default, Bits Access 7:0 00h 3.5.9 HDR—Header Type Register (D0:F0) Address Offset: Default: ...
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Register Description 3.5.11 SID—Subsystem Identification Register (D0:F0) Address Offset: Default: Access: Size: This value is used to identify a particular subsystem. Default, Bits Access 0000h 15:0 R/WO 3.5.12 CAPPTR—Capabilities Pointer Register (D0:F0) Address Offset: Default: Access: Size: This register provides ...
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MCHCAP—MCH Capabilities Structure Register (D0:F0) Address Offset: Default: Access: Size: This register provides the capabilities information for the MCH. Default, Bits Access 39:29 000h 27:24 RO 05h 23:16 RO 00h 15:8 RO 09h 7:0 RO ...
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Register Description Default, Bits Access 12:6 0000000b Description Reserved MDA Present (MDAP). This bit works with the VGA enable bits in the BCTRL ...
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MCHCFGNS—MCH Configuration Register (D0:F0) Address Offset: Default: Access: Size: This register controls the mode and status of the DRAM memory scrubber. Default, Bits Access 15:4 000h 00b 2:1 R R/W 3.5.16 FDHC—Fixed DRAM Hole ...
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Register Description 3.5.17 PAM[6:0]—Programmable Attribute Map Registers (D0:F0) Address Offset: Default: Access: Size: The MCH allows programmable memory attributes on 13 legacy memory segments of various sizes in the 768-KB to 1-MB address range. Seven Programmable Attribute Map (PAM) registers ...
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Figure 3-1. PAM Registers rite ble ( ble Table 3-3. PAM Associated Attribute Bits PAM ...
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Register Description 3.5.18 DRB[0:7]—DRAM Row Boundary Register (D0:F0) Address Offset: Default: Access: Size: The DRAM Row Boundary Register defines the upper boundary address of each DRAM row with a granularity dual-channel mode ...
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DRA[3:0]—DRAM Row Attribute Register (D0:F0) Address Offset: Default: Access: Size: The DRAM Row Attribute Register defines the page sizes to be used for each row of memory. Each nibble of information in the DRA registers describes the page size ...
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Register Description 3.5.20 DRT—DRAM Timing Register (D0:F0) Address Offset: Default: Access: Size: This register controls the timing of the DRAM controller. Default, Bits Access 31:30 00b R/W 000b 26:24 R/W 23:19 00h ...
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Default, Bits Access 000b 18:16 R/W 15:11 00h 00b 10:9 R/W 8:6 000b 01b 5:4 R R/W 00b 2:1 R R/W ® Intel E7501 Chipset MCH Datasheet Description DRAM Idle Timer. This field determines the number ...
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Register Description 3.5.21 DRC—DRAM Controller Mode Register (D0:F0) Address Offset: Default: Access: Size: This register controls the mode of the DRAM controller. Default, Bits Access 31:30 00b 0b 29 R/W 28:23 00h 1b 22 R/W 00b 21:20 R/W 01b 19:18 ...
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Default, Bits Access 7 0b 000b 6:4 R/W 3:0 9h 3.5.22 CKDIS—CK / CK# Disable Register (D0:F0) Address Offset: Default: Access: Size: Default, Bits Access 1b 7 R/W 6 3:0 R/W ® Intel E7501 Chipset MCH Datasheet Description ...
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Register Description 3.5.23 CFGCTL—Configuration Control Register (D0:F0) Address Offset: Default: Access: Size: This register may only be written to at boot time when there is no traffic to or from the HI. The MCH does not support turning off a ...
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SMRAMC—System Management RAM Control Register (D0:F0) Address Offset: Default: Access: Size: The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The open, close, and lock bits function only when G_SMRAME bit is set to ...
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Register Description 3.5.25 ESMRAMC—Extended System Management RAM Control Register (D0:F0) Address Offset: Default: Access: Size: The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is ...
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TOLM—Top of Low Memory Register (D0:F0) Address Offset: Default: Access: Size: This register contains the maximum address below 4 GB that should be treated as main memory, and is defined on a 128-MB boundary. Normally set below ...
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Register Description 3.5.28 REMAPLIMIT—Remap Limit Address Register (D0:F0) Address Offset: Default: Access: Size: This register specifies the upper boundary of the remap window. Default, Bits Access 15:10 00h 000h 9:0 R/W 3.5.29 SKPD—Scratchpad Data Register (D0:F0) Address Offset: Default: Access: ...
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DVNP—Device Not Present Register (D0:F0) Address Offset: Default: Access: Size: This register is used to control whether the Function 1 portions of the PCI configuration space for Devices are visible to software device’s ...
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Register Description 3.6 Host RASUM Controller Registers (Device 0, Function 1) This section describes the DRAM Controller registers for Device 0 (D0), Function 1 (F1). Table 3-4 provides the register address map for this device, function. Warning: Address locations that ...
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VID—Vendor Identification Register (D0:F1) Address Offset: Default: Sticky Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Default, Bits Access 8086h 15:0 RO 3.6.2 ...
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Register Description 3.6.3 PCICMD—PCI Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: Since MCH Device 0 does not physically reside on a physical PCI bus, portions of this register are not implemented. Default, Bits Access 15:9 00h 0b 8 ...
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PCISTS—PCI Status Register (D0:F1) Address Offset: Default: Sticky: Access: Size: PCISTS is a 16-bit status register that reports the occurrence of error events on Device 0’s PCI interface. Since MCH Device 0 does not physically reside on a PCI ...
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Register Description 3.6.6 SUBC—Sub-Class Code Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register contains the Sub-Class Code for the MCH Device 0, Function 1. Default, Bits Access 00h 7:0 RO 3.6.7 BCC—Base Class Code Register (D0:F1) Address Offset: ...
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HDR—Header Type Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register identifies the header layout of the configuration space. Default, Bits Access 00h 7:0 RO 3.6.10 SVID—Subsystem Vendor Identification Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This ...
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Register Description 3.6.12 FERR_GLOBAL—First Global Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register is used to report various error conditions. A SERR is generated on a 0-to-1 transition of any of these flags (if enabled by the ...
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NERR_GLOBAL—Next Global Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: The FIRST global error will be stored in FERR_GLOBAL. This register stores all future global errors. Multiple bits in this register may be set. Note: To prevent the ...
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Register Description 3.6.14 HIA_FERR—HI_A First Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register stores the FIRST error related to the HI_A interface. Any number of errors detected in a single clock cycle will be latched and no ...
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HIA_NERR—HI_A Next Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: The FIRST HI_A error will be stored in HIA_FERR. This register stores all future HI_A errors. Multiple bits in this register may be set. Note: Software must write ...
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Register Description 3.6.16 SCICMD_HIA—SCI Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SCI will be generated when the associated flag is set in HIA_FERR or HIA_NERR. When an error flag is set in the HIA_FERR ...
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SMICMD_HIA—SMI Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SMI will be generated when the associated flag is set in HIA_FERR or HIA_NERR. When an error flag is set in the HIA_FERR or HIA_NERR ...
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Register Description 3.6.18 SERRCMD_HIA—SERR Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SERR will be generated when the associated flag is set in HIA_FERR or HIA_NERR. When an error flag is set in the HIA_FERR ...
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SYSBUS_FERR—System Bus First Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register stores the FIRST error related to the system bus interface. Any number of errors detected in a single clock cycle will be latched and no ...
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Register Description 3.6.20 SYSBUS_NERR— System Bus Next Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: The FIRST system bus error will be stored in SYSBUS_FERR. This register stores all future system bus errors. Multiple bits in this register may ...
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SCICMD_SYSBUS—SCI Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SCI will be generated when the associated flag is set in SYSBUS_FERR or SYSBUS_NERR. When an error flag is set in the SYSBUS_FERR or SYSBUS_NERR ...
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Register Description 3.6.22 SMICMD_SYSBUS—SMI Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SMI will be generated when the associated flag is set in SYSBUS_FERR or SYSBUS_NERR. When an error flag is set in the SYSBUS_FERR ...
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SERRCMD_SYSBUS—SERR Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SERR will be generated when the associated flag is set in SYSBUS_FERR or SYSBUS_NERR. When an error flag is set in the SYSBUS_FERR or SYSBUS_NERR ...
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Register Description 3.6.24 DRAM_FERR—DRAM First Error Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register stores the FIRST ECC error on the DRAM interface. Any number of errors detected in a single clock cycle will be latched and no ...
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SCICMD_DRAM—SCI Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register determines whether SCI will be generated when the associated flag is set in DRAM_FERR or DRAM_NERR. When an error flag is set in the DRAM_FERR or DRAM_NERR ...
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Register Description 3.6.28 SERRCMD_DRAM—SERR Command Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register detemines whether SERR will be generated when the associated flag is set in DRAM_FERR or DRAM_NERR. When an error flag is set in the DRAM_FERR ...
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DRAM_UELOG_ADD—DRAM First Uncorrectable Memory Error Address Register (D0:F1) Address Offset: Default: Sticky: Access: Size: This register contains the physical address of the first uncorrectable memory error. When a flag in either DRAM_FERR or DRAM_NERR is set, DRAM_UELOG_ADD is locked. ...
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Register Description 3.7 Hub Interface_B PCI-to-PCI Bridge Registers (Device 2, Function 0) This section provides the register descriptions for the Hub Interface_B PCI-to-PCI bridge (Device 2, Function 0). Warning: Address locations that are not listed in the table are considered ...
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VID—Vendor Identification Register (D2:F0) Address Offset: Default: Sticky: Access: Size: The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identifies any PCI device. Default, Bits Access 8086h 15:0 RO 3.7.2 ...
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Register Description 3.7.3 PCICMD—PCI Command Register (D2:F0) Address Offset: Default: Sticky: Access: Size: Since MCH Device 0 does not physically reside on a physical PCI bus, portions of this register are not implemented. Default, Bits Access 15:10 00h 0b 9 ...
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PCISTS—PCI Status Register (D2:F0) Address Offset: Default: Sticky: Access: Size: PCISTS2 is a 16-bit status register that reports the occurrence of error conditions associated with the primary side of the “virtual” PCI-to-PCI bridge embedded within the MCH. Default, Bits ...
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Register Description 3.7.5 RID—Revision Identification Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register contains the revision number of the MCH Device 2. Default, Bits Access 00h 7:0 RO 3.7.6 SUBC—Sub-Class Code Register (D2:F0) Address Offset: Default: Sticky: Access: ...
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MLT—Master Latency Timer Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This functionality is not applicable described here since these bits should be implemented as read/write to ensure proper execution of standard PCI-to-PCI bridge configuration software. Default, ...
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Register Description 3.7.10 PBUSN—Primary Bus Number Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register identifies that a “virtual” PCI-to-PCI bridge is connected to Bus 0. Default, Bits Access 00h 7:0 RO 3.7.11 SBUSN—Secondary Bus Number Register (D2:F0) Address ...
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SUBUSN—Subordinate Bus Number Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register identifies the highest subordinate bus (if any) that resides at the level below the secondary hub interface. This number is programmed by the PCI configuration software ...
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Register Description 3.7.14 IOBASE—I/O Base Address Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register controls the processor-to-HI_B I/O access routing based on the following formula: IO_BASE < address < IO_LIMIT Only the upper four bits are programmable. For ...
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SEC_STS—Secondary Status Register (D2:F0) Address Offset: Default: Sticky: Access: Size: SEC_STS is a 16-bit status register that reports the occurrence of error conditions associated with the secondary side (i.e., HI_B side) of the “virtual” PCI-to-PCI bridge embedded within the ...
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Register Description 3.7.17 MBASE—Memory Base Address Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register controls the processor-to-HI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE < address < MEMORY_LIMIT The upper 12 bits of the register ...
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MLIMIT—Memory Limit Address Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register controls the processor-to-HI_B non-prefetchable memory access routing based on the following formula: MEMORY_BASE < address < MEMORY_LIMIT The upper 12 bits of the register are read/write ...
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Register Description 3.7.19 PMBASE—Prefetchable Memory Base Address Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register controls the processor-to-HI_B prefetchable memory accesses. The upper 12 bits of the register are read/write and correspond to the upper 12 address bits ...
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BCTRL—Bridge Control Register (D2:F0) Address Offset: Default: Sticky: Access: Size: This register provides extensions to the PCICMD register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., HI_B) as well as some ...
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Register Description 3.8 Hub Interface_B PCI-to-PCI Bridge Error Reporting Registers (Device 2, Function 1) This section provides the register descriptions for the Hub Interface_B PCI-to-PCI bridge (Device 2, Function 1). Warning: Address locations that are not listed in the table ...
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VID—Vendor Identification Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: The VID register contains the vendor identification number. This 16-bit register combined with the Device Identification register uniquely identifies any PCI device. Default, Bits Access 8086h 15:0 ...
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Register Description 3.8.3 PCICMD—PCI Command Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: Since MCH Device 2 does not physically reside on a physical PCI bus, portions of this register are not implemented. Default, Bits Access 15:9 00h ...
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RID—Revision Identification Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: This register contains the revision number of the MCH Device 2. Default, Bits Access 00h 7:0 RO 3.8.6 SUBC—Sub-Class Code Register (D2:F1) Address Offset: Default: Sticky: Access: ...
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Register Description 3.8.7 BCC—Base Class Code Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: This register contains the Base Class Code of the MCH Device 2. Default, Bits Access FFh 7:0 RO 3.8.8 HDR—Header Type Register (D2:F1) Address ...
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SVID—Subsystem Vendor Identification Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: This value is used to identify the vendor of the subsystem. Default, Bits Access 0000h 15:0 R/WO 3.8.10 SID—Subsystem Identification Register (D2:F1) Address Offset: Default: Sticky: ...
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Register Description 3.8.11 HIB_FERR—HI_B First Error Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: This register stores the FIRST error related to the HI_B interface. Only one error bit will be set in this register. Any future errors ...
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HIB_NERR—HI_B Next Error Register (D2:F1) Address Offset: Default: Sticky: Access: Size: SMB Shadowed: The FIRST error related to HI_B will be stored in HIB_FERR. This register stores all future errors related to the HI_B interface. Multiple bits in this ...
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Register Description 3.8.13 SERRCMD—SERR Command Register (D2:F1) Address Offset: Default: Sticky: Access: Size: This register detemines whether a SERR will be generated when the associated flag is set in HIB_FERR or HIB_NERR. When an error flag is set in the ...
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SMICMD—SMI Command Register (D2:F1) Address Offset: Default: Sticky: Access: Size: This register detemines whether an SMI will be generated when the associated flag is set in HIB_FERR or HIB_NERR. When an error flag is set in the HIB_FERR or ...
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Register Description 3.8.15 SCICMD—SCI Command Register (D2:F1) Address Offset: Default: Sticky: Access: Size: This register detemines whether an SCI will be generated when the associated flag is set in HIB_FERR or HIB_NERR. When an error flag is set in the ...
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Hub Interface_C PCI-to-PCI Bridge Registers (Device 3, Function 0, 1) Device 3 is the HI_C virtual PCI-to-PCI bridge. The register descriptions for Device 3 are the same as Device 2 (except for the DID Registers). This section contains the ...
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Register Description Table 3-8. Hub Interface_C PCI-to-PCI Bridge Error Reporting Register Map (HI_C—D3:F1) Offset Mnemonic 00–01h 02–03h 04–05h PCICMD 06–07h PCISTS 08h 0Ah SUBC 0Bh BCC 0Eh HDR 2C–2Dh SVID 2E–2Fh 80h HIC_FERR 82h HIC_NERR A0h SERRCMD A2h SMICMD A4h ...
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Hub Interface_D PCI-to-PCI Bridge Registers (Device 4, Function 0, 1) Device 4 is the HI_D virtual PCI-to-PCI bridge. The register descriptions for Device 4 are the same as Device 2 (except for the DID Registers). This section contains register ...
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Register Description Table 3-10. Hub Interface_D PCI-to-PCI Bridge Error Reporting Register Map (HI_D—D4:F1) Offset Mnemonic 00–01h 02–03h 04–05h PCICMD 06–07h PCISTS 08h 0Ah SUBC 0Bh BCC 0Eh HDR 2C–2Dh SVID 2E–2Fh 80h HID_FERR 82h HID_NERR A0h SERRCMD A2h SMICMD A4h ...
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System Address Map A system based on the E7501 chipset in dual-channel mode supports 16 GB – host- addressable memory space. In single-channel mode, it supports 8 GB – host-addressable memory space. It also ...
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System Address Map These address ranges are always mapped to system memory, regardless of the system configuration. Memory may be allocated from the system memory segment for use by System Management Mode (SMM) hardware and software. The top of system ...
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VGA and MDA Memory Spaces Video cards use these legacy address ranges to map a frame buffer or a character-based video buffer. The address ranges in this memory space are: • VGAA 0_000A_0000h to 0_000A_FFFFh • MDA 0_000B_0000h to ...
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System Address Map The 256-KB PAM region is divided into three parts: • ISA expansion region: a 128-KB area between 0_000C_0000h to 0_000D_FFFFh • Extended BIOS region: a 64-KB area between 0_000E_0000h to 0_000E_FFFFh • System BIOS region: a 64-KB ...
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I/O APIC Memory Space The I/O APIC spaces are used to communicate with I/O APIC interrupt controllers that may be populated on HI_A through HI_D. Since it is difficult to relocate an interrupt controller using plug- and-play software, fixed ...
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System Address Map 4.1.9 Device 3 Memory and Prefetchable Memory Plug-and-play software configures the HI_C memory window to provide enough memory space for the devices behind this PCI-to-PCI bridge. Accesses that have addresses that fall within this window are decoded ...
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SMM Space 4.3.1 System Management Mode (SMM) Memory Range The E7501 chipset supports the use of system memory as System Management Mode RAM (SMM RAM), which enables the use of System Management Mode. The MCH supports three SMM options: ...
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System Address Map Table 4-1. SMM Address Range SMM Space Enabled Compatible 1 High 2 TSEG NOTES: 1. High SMM: This is different than in previous chipsets. In previous chipsets the High segment was the 384-KB region from A_0000h to ...
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Functional Description This chapter covers the MCH functional units including: system bus, system memory, SMBus, power management, MCH clocking, MCH system reset and power sequencing. 5.1 Processor System Bus (PSB) The MCH supports the Intel processor with 533 MHz system ...
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Functional Description 5.1.3 System Bus Dynamic Inversion The MCH supports Dynamic Bus Inversion (DBI) both when driving and when receiving data from the system bus. DBI limits the number of data signals that are driven to a low voltage on ...
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The MCH accepts message based interrupts from its hub interface and forwards them to the system bus as Interrupt Message Transactions. The interrupt messages presented to the MCH are in the form of memory writes to address 0FEEx_xxxxh. At the ...
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Functional Description 5.5 System Memory Controller The MCH can support DDR 266 and DDR 200 using SSTL_2 signaling. The MCH includes support for: • In dual-channel mode 266 MHz or 200 MHz DDR SDRAM installed ...
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For the DDR SDRAM interface, that the MCH supports configurations defined in the JEDEC DDR DIMM specification only (A,B,C). For more information on DIMM configurations, refer to the JEDEC DDR DIMM specification. Table 5-2. Memory per DIMM at Each DRAM ...
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Functional Description 5.5.3 Memory Address Translation and Decoding The MCH contains address decoders that translate the address received on the host bus or the hub interface. Decoding and translation of these addresses vary with the three SDRAM devices. Also, the ...
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Table 5-4. Address Translation and Decoding in Single-Channel Mode 8 Meg 12 256 MB Row 128 Col x 4 bks Meg 12 128 MB Row 128 ...
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Functional Description 5.5.5 DDR Clock Generation The MCH drives the clocks to the DIMMs. Registered DIMMs require one clock pair per DIMM. A motherboard can implement three DIMMs per channel, or four DIMMs per channel. The following table provides the ...
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Thermal Management Parameters While the software forced thermal management and counter mechanism settings determine when to thermal manage, additional bits determine how much to thermal manage. Once thermal management is invoked, users can specify with precise granularity how many ...
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Functional Description 5.6 Power and Thermal Management The chipset supports the ACPI 1.0 system states: S0, S1, S5, C0, C1, and C2. 5.6.1 Processor Power State Control • C0 (Full On): This is the only state that runs software. All ...
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Clocking Figure 5-1 shows a block diagram of an E7501 chipset-based system. The MCH has the following clocks: • 100/133 MHz, Spread spectrum, Low voltage (0.7 V) Differential HCLKINP/HCLKINN for PSB • 66.667 MHz, Spread spectrum, 3.3 V CLK66 ...
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Functional Description 5.8 RASUM Features 5.8.1 DRAM ECC In dual-channel mode, the ECC used for DRAM provides S4EC/D4ED x4 Single Device Data Correction (SDDC) technology protection for x4 SDRAMs, but not for x8 DRAMs. In single- channel mode and x8 ...
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Electrical Characteristics This chapter provides the absolute maximum ratings, thermal characteristics, and DC characteristics for the MCH. 6.1 Absolute Maximum Ratings Table 6-1 lists the E7501 chipset MCH’s maximum environmental stress ratings. Functional operation at the absolute maximum and minimum ...
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Electrical Characteristics 6.3 Power Characteristics Table 6-2. DC Characteristics Functional Operating Range Symbol I 1.2 V MCH Core and HI CC 1.525 V AGTL+ I VTT 1.102 V AGTL+ I 2.5 V Vdd DDR dd_DDR NOTES: 1. When using the ...
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Table 6-4. DDR Interface Signal Groups Signal Signal Type Group (h) SSTL-2 I/O (i) SSTL-2 Output (j) Analog Input NOTE DDR channel Table 6-5. Hub Interface 2.0 (HI_B, HI_C, HI_D) Signal Groups Signal Signal ...
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Electrical Characteristics 6.4.2 DC Characteristics at VCC1_2 = 1.2 V ± 5% Table 6-9. Operating Condition Supply Voltage Signal Symbol Group VTT (g) Host AGTL+ Termination Voltage VCC2_5 DDR Buffer Voltage VCC1_2 MCH Core Voltage NOTES: ® 1. When using ...
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System Bus Interface DC Characteristics Table 6-10. System Bus Interface DC Characteristics Signal Symbol Parameter Group V (a), (c) Host AGTL+ Input Low Voltage IL_H V (a), (c) Host AGTL+ Input High Voltage IH_H V (a), (b) Host AGTL+ ...
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Electrical Characteristics 6.4.4 DDR Interface DC Characteristics Table 6-11. DDR Interface DC Characteristics Signal Symbol Group V (h) DDR Input Low DC Voltage IL (DC) V (h) DDR Input High DC Voltage IH (DC) V (h) DDR Input Low AC ...
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Hub Interface 2.0 DC Characteristics Table 6-12. Hub Interface 2.0 DC Characteristics Signal Symbol Group V (k) Hub Interface Input Low Voltage IL_HI V (k) Hub Interface Input High Voltage IH_HI V (k) Hub Interface Output Low Voltage OL_HI ...
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Electrical Characteristics 6.4.6 Hub Interface 1.5 DC Characteristics Table 6-13. Hub Interface 1.5 DC Characteristics Signal Symbol Group V (n) Hub Interface Input Low Voltage IL_HI V (n) Hub Interface Input High Voltage IH_HI V (n) Hub Interface Output Low ...
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SMBus DC Characteristics Table 6-14. SMBus DC Characteristics Signal Symbol Group V (q) SMBus Input Low Voltage IL_SMB V (q) SMBus Input High Voltage IH_SMB V (q) SMBus Output Low Voltage OL_SMB I (q) SMBus Input Leakage Current IL_SMB ...
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Electrical Characteristics 138 ® Intel E7501 Chipset MCH Datasheet ...
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Ballout and Package Specifications This chapter provides the ballout and package dimensions for the E7501 MCH. In addition, internal component package trace lengths to enable trace length compensation are listed. 7.1 Ballout Figure 7-1 shows a top view of the ...
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Ballout and Package Specifications Figure 7-1. MCH Ballout (left half of top view VSS VCC2_5 DQ_A4 AM VCC2_5 MA_A12 MA_A9 VSS AL VSS DQ_B60 BA_A0 VSS MA_A7 AK VCC2_5 CS_B1# VSS MA_A11 MA_A8 AJ ...
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Figure 7-2. MCH Ballout (right half of top view VSS VCC2_5 DQ_A37 DQ_A42 DDRVREF CB_A6 VSS DQ_A33 DQS_A5 _A2 CB_A2 VCC2_5 DQ_A32 DQS_A4 VSS VSS CB_A3 DQ_A36 VSS DQS_A14 DQS_A8 DQ_A34 VCC2_5 DQS_A13 DQ_A46 ...
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Ballout and Package Specifications Figure 7-3. MCH Ballout (top view ...
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Table 7-1. Ballout by Signal Name Signal Name ADS# AP0# AP1# BA_A0 BA_A1 BA_B0 BA_B1 BINIT# BNR# BPRI# BREQ0# CAS_A# CAS_B# CB_A0 CB_A1 CB_A2 CB_A3 CB_A4 CB_A5 CB_A6 CB_A7 CB_B0 CB_B1 CB_B2 CB_B3 CB_B4 CB_B5 CB_B6 CB_B7 CKE_A CKE_B CLK66 ...
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Ballout and Package Specifications Table 7-1. Ballout by Signal Name Signal Name DQ_A45 DQ_A46 DQ_A47 DQ_A48 DQ_A49 DQ_A50 DQ_A51 DQ_A52 DQ_A53 DQ_A54 DQ_A55 DQ_A56 DQ_A57 DQ_A58 DQ_A59 DQ_A60 DQ_A61 DQ_A62 DQ_A63 DQ_B0 DQ_B1 DQ_B2 DQ_B3 DQ_B4 DQ_B5 DQ_B6 DQ_B7 DQ_B8 ...
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Table 7-1. Ballout by Signal Name Signal Name HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HA32# HA33# HA34# HA35# HADSTB0# HADSTB1# HAVREF0 HAVREF1 HCCVREF HCLKINN HCLKINP HD0# HD1# HD2# HD3# ...
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Ballout and Package Specifications Table 7-1. Ballout by Signal Name Signal Name HI_B16 HI_B17 HI_B18 HI_B20 HI_B21 HI_C0 HI_C1 HI_C2 HI_C3 HI_C4 HI_C5 HI_C6 HI_C7 HI_C8 HI_C9 HI_C10 HI_C11 HI_C12 HI_C13 HI_C14 HI_C15 HI_C16 HI_C17 HI_C18 HI_C20 HI_C21 HI_D0 HI_D1 ...
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Table 7-1. Ballout by Signal Name Signal Name RSP# RSTIN# SMB_CLK SMB_DATA VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU VCC_CPU ...
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Ballout and Package Specifications Table 7-1. Ballout by Signal Name Signal Name VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 VCC2_5 ...
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Table 7-1. Ballout by Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...
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Ballout and Package Specifications Table 7-1. Ballout by Signal Name Signal Name VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 150 ...
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Package Specifications Figure 7-4 and Figure 7-5 Figure 7-4. MCH Package Dimensions (Top View ...
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Ballout and Package Specifications Figure 7-5. MCH Package Dimensions (Side View) 1.940 ± 0.150 mm 0.60 ± 0.10 mm NOTES: 1. All dimensions are in millimeters. 2. Substrate thickness and package overall height are thicker than standard 492-L-PBGA 3. Primary ...
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Chipset Interface Trace Length Compensation In this section, detailed information is given about the internal component package trace lengths to enable trace length compensation. Trace length compensation is required for platform design. These lengths must be considered when matching ...
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Ballout and Package Specifications 7.3.1 System Bus Signal Package Trace Length Data Table 7-3 provides the MCH package trace length information for the system bus. Table 7-3. MCH L Data for the System Bus (Sheet PKG Signal ...
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Table 7-3. MCH L Data for the System Bus (Sheet PKG Signal Ball No. HA29# AF3 HA30# AF7 HA31# AH5 HA32# AG7 HA33# AH6 HA34# AJ1 HA35# AG5 HCLKINN U3 HCLKINP T2 HDSTBN2# J2 HDSTBP2# J4 HD32# ...
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Ballout and Package Specifications 7.3.2 MCH DDR Channel A Signal Package Trace Length Data Table 7-4 provides the MCH package trace length information for channel A of the DDR memory interface. Table 7-4. MCH L Data for DDR Channel A ...
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Table 7-4. MCH L Data for DDR Channel A (Sheet PKG Signal DQS_A5 AM12 DQS_A14 AK12 DQ_A40 AE14 DQ_A41 AH13 DQ_A42 AN12 DQ_A43 AL11 DQ_A44 AE15 DQ_A45 AF13 DQ_A46 AJ12 DQ_A47 AM10 DQS_A6 AL8 DQS_A15 AM7 DQ_A48 ...
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Ballout and Package Specifications 7.3.3 MCH DDR Channel B Signal Package Trace Length Data Table 7-5 provides the MCH package trace length information for channel B of the DDR memory interface. Table 7-5. MCH L Data for DDR Channel B ...
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Table 7-5. MCH L Data for DDR Channel B (Sheet PKG Signal DQS_B6 DQS_B15 DQ_B48 DQ_B49 DQ_B50 DQ_B51 DQ_B52 DQ_B53 DQ_B54 DQ_B55 DQS_B7 DQS_B16 DQ_B56 DQ_B57 DQ_B58 DQ_B59 DQ_B60 DQ_B61 DQ_B62 DQ_B63 ® Intel E7501 Chipset MCH ...
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Ballout and Package Specifications 7.3.4 MCH Hub Interface_B Signal Package Trace Length Data Table 7-6 provides the MCH package trace length information for Hub Interface_B. Table 7-6. MCH L Data for Hub Interface_B PKG Signal PSTRBF_B PSTRBS_B HI_B0 HI_B1 HI_B2 ...
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MCH Hub Interface_D Signal Package Trace Length Data Table 7-8 provides the MCH package trace length information for Hub Interface_D. Table 7-8. MCH L Data for Hub Interface_D PKG Signal PSTRBF_D D27 PSTRBS_D D26 HI_D0 D28 HI_D1 G25 HI_D2 ...
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Ballout and Package Specifications 162 This page is intentionally left blank. ® Intel E7501 Chipset MCH Datasheet ...
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Testability For Automated Test Equipment (ATE) the MCH supports XOR-tree testing. XOR-tree testing allows board-level interconnections to be tested. An XOR-Tree is a chain of XOR gates, with each having one input pin or one bi-directional pin (used as an ...
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Testability 8.2 XOR Chains The XOR chain outputs (XOR chains 8 through 1) are visible on HI_A[7:0]. In Long XOR chain mode the delay through the 4 pad ring chains (chains may be observed on HI_A4. ...
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Table 8-1. XOR Chains (Sheet Chain #1 Chain #2 Chain #3 DQ_A41 DQ_A1 DQ_B35 DQS_A14 DQS_A9 DQS_B13 DQ_A46 DQ_A5 DQ_B36 DQ_A44 DQ_A4 DQ_B39 DQ_A45 DQ_A7 DQ_B38 DQ_A47 DQ_A6 DQ_B37 DQS_A5 DQS_A0 DQS_B4 DQ_A40 DQ_A3 DQ_B34 DQ_A43 DQ_A2 ...
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Testability Table 8-1. XOR Chains (Sheet Chain #1 Chain #2 Chain #3 DQ_A22 DQ_B23 DQ_A23 DQ_B22 DQS_A2 DQS_B2 DQ_A18 DQ_B18 DQ_A19 DQ_B17 Out = HI_A0 Out = HI_A1 Out = HI_A2 166 Chain #4 Chain #5 Chain ...