AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet - Page 33

• Manufacturer Part Number: AT89C51CC03
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC03

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 37
• Spi: 1
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Power Management
Introduction
Idle Mode
Entering Idle Mode
Exiting Idle Mode
Power-Down Mode
4182O–CAN–09/08
Two power reduction modes are implemented in the AT89C51CC03. The Idle mode and
the Power-Down mode. These modes are detailed in the following sections. In addition
to these power reduction modes, the clocks of the core and peripherals can be dynami-
cally divided by 2 using the X2 mode detailed in Section “Clock”, page 17.
Idle mode is a power reduction mode that reduces the power consumption. In this mode,
program execution halts. Idle mode freezes the clock to the CPU at known states while
the peripherals continue to be clocked. The CPU status before entering Idle mode is
preserved, i.e., the program counter and program status word register retain their data
for the duration of Idle mode. The contents of the
status of the Port pins during Idle mode is detailed in Table 9.
To enter Idle mode, set the IDL bit in PCON register (see Table 10). The AT89C51CC03
enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that
sets IDL bit is the last instruction executed.
Note:
There are two ways to exit Idle mode:
1. Generate an enabled interrupt.
2. Generate a reset.
Note:
The Power-Down mode places the AT89C51CC03 in a very low power state. Power-
Down mode stops the oscillator, freezes all clock at known states. The CPU status prior
to entering Power-Down mode is preserved, i.e., the program counter, program status
word register retain their data for the duration of Power-Down mode. In addition, the
and RAM contents are preserved. The status of the Port pins during Power-Down mode
is detailed in Table 9.
Note:
–
–
If IDL bit and PD bit are set simultaneously, the AT89C51CC03 enters Power-Down
mode. Then it does not go in Idle mode when exiting Power-Down mode.
Hardware clears IDL bit in PCON register which restores the clock to the
CPU. Execution resumes with the interrupt service routine. Upon completion
of the interrupt service routine, program execution resumes with the
instruction immediately following the instruction that activated Idle mode.
The general purpose flags (GF1 and GF0 in PCON register) may be used to
indicate whether an interrupt occurred during normal operation or during Idle
mode. When Idle mode is exited by an interrupt, the interrupt service routine
may examine GF1 and GF0.
A logic high on the RST pin clears IDL bit in PCON register directly and
asynchronously. This restores the clock to the CPU. Program execution
momentarily resumes with the instruction immediately following the
instruction that activated the Idle mode and may continue for a number of
clock cycles before the internal reset algorithm takes control. Reset
initializes the AT89C51CC03 and vectors the CPU to address C:0000h.
During the time that execution resumes, the internal RAM cannot be accessed; however,
it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port
pins, the instruction immediately following the instruction that activated Idle mode should
not write to a Port pin or to the external RAM.
VCC may be reduced to as low as V
power dissipation. Take care, however, that VDD is not reduced until Power-Down mode
is invoked.
RET
during Power-Down mode to further reduce
SFRs
and RAM are also retained. The
AT89C51CC03
SFR
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