AT90USB646 Atmel Corporation, AT90USB646 Datasheet - Page 344
AT90USB646
Manufacturer Part Number
AT90USB646
Description
Manufacturer
Atmel Corporation
Specifications of AT90USB646
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
48
Ext Interrupts
16
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
2
Twi (i2c)
1
Uart
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
10
Input Capture Channels
1
Pwm Channels
9
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB646-AU
Manufacturer:
MOT
Quantity:
1 100
Part Number:
AT90USB646-AU
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Part Number:
AT90USB646-MU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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27.6.2
344
AT90USB64/128
Scanning the RESET Pin
Figure 27-4. General Port Pin Schematic Diagram
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
inserted for the 5V reset signal.
Figure 27-5. Observe-only Cell
See Boundary-scan
Description for Details!
Pxn
From System Pin
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
IDxn
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
Previous
From
PUExn
Cell
ShiftDR
0
1
ClockDR
SLEEP
OCxn
ODxn
D
FF1
SYNCHRONIZER
D
L
WDx:
RDx:
WRx:
RRx:
RPx:
CLK
Q
Q
Q
Next
I/O
Cell
To
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
Q
Q
To System Logic
RESET
RESET
Q
Q
Q
Q
PORTxn
DDxn
CLR
CLR
D
D
CLK
PUD
WRx
WDx
RDx
RRx
RPx
I/O
Figure 27-5
7593K–AVR–11/09
is
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