ATtiny25 Automotive Atmel Corporation, ATtiny25 Automotive Datasheet
ATtiny25 Automotive
Specifications of ATtiny25 Automotive
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ATtiny25 Automotive Summary of contents
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation • Non-volatile Program and Data Memories – ...
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Pin Configurations Figure 1-1. Pinout ATtiny25/45/85 (PCINT5/RESET/ADC0/dW) PB5 (PCINT3/XTAL1/OC1B/ADC3) PB3 (PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4 2. Overview The ATtiny25/45/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ...
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Block Diagram Figure 2-1. VCC GND The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be ...
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The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed Timer/Counter, Universal ...
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Pin Descriptions 2.3.1 VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB5..PB0) Port 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with ...
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Architectural Overview Figure 4-1. In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. ...
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The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic opera- tion, the Status Register is updated to reflect information about ...
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Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter- rupt enable control is then performed in separate control registers. If the Global Interrupt Enable ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...
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Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used. Figure 4-4 vard architecture and the fast access ...
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When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis- abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt ...
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. Assembly Code Example sei sleep; enter sleep, waiting for interrupt ; note: will enter sleep ...
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Figure 5-1. 5.2 SRAM Data Memory Figure 5-2 The lower 224/352/607 Data memory locations address both the Register File, the I/O memory and the internal data SRAM. The first 32 locations address the Register File, the next 64 loca- tions ...
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Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 5-3. 5.3 EEPROM Data Memory The ATtiny25/45/85 contains 128/256/512 bytes of data ...
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EEPROM Address Register High – EEARH Bit Read/Write Initial Value • Bit 7..1 – Res6..0: Reserved Bits These bits are reserved for future use and will always read ATtiny25/45/85. • Bits 0 – EEAR8: EEPROM Address ...
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Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny25/45/85 and will always read as zero. • Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bits setting defines which ...
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Atomic Byte Programming Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn bits are zero, ...
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Assembly Code Example EEPROM_write: C Code Example void EEPROM_write(unsigned char ucAddress, unsigned char ucData 7598H–AVR–07/09 ; Wait for completion of previous write sbic EECR,EEPE rjmp EEPROM_write ; Set Programming mode ldi r16, (0<<EEPM1)|(0<<EEPM0) EECR, r16 out ; Set ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...
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I/O Memory The I/O space definition of the ATtiny25/45/85 is shown in All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...
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CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory ...
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Figure 6-2. 6.2 Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. ...
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Table 6-2. 6.3 Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up time and ...
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Table 6-4. CKSEL0 Notes: 6.5 Low-frequency Crystal Oscillator To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal oscillator must be selected by setting CKSEL ...
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Calibrated Internal RC Oscillator The calibrated internal RC Oscillator provides an 8.0 MHz clock. The frequency is the nominal value at 3V and 25°C. If the frequency exceeds the specification of the device (depends on V the CKDIV8 Fuse ...
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The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre- quency ranges are overlapping, in other ...
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Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to 29 for details. 6.7.1 High Frequency PLL Clock - PLL There is an internal PLL ...
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Clock Output Buffer The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir- ...
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The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of eight at ...
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Power Management and Sleep Modes The high performance and industry leading code efficiency makes the AVR microcontrollers an ideal choise for low power applications. Sleep modes enable the application to shut down unused modules in the MCU, thereby saving ...
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Table 7-1. • Bit 2 – BODSE: BOD Sleep Enable BOD disable functionality is available in some devices, only. See The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD disable is controlled by ...
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Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to for details Table 7-2. Sleep Mode Idle ADC Noise Reduction ...
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Bit 2- PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 - PRUSI: Power Reduction USI Writing ...
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Watchdog Timer If the Watchdog Timer is not needed in the application, this module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the ...
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Figure 8-1. BODLEVEL [1..0] 8.3 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in POR circuit can be used to trigger the Start-up Reset, as well as to detect ...
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Figure 8- TIME-OUT INTERNAL RESET Figure 8- RESET TIME-OUT INTERNAL RESET Table 8-1. Symbol V POT V PORMAX V PORMIN V CCRR V RST Note: 8.4 External Reset An External Reset is generated by a low ...
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Figure 8-4. 8.5 Brown-out Detection ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. ...
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When the BOD is enabled, and V 8-5), the Brown-out Reset is immediately activated. When V (V BOT+ expired. The BOD circuit will only detect a drop in V ger than t Figure 8-5. 8.6 Watchdog Reset When the Watchdog ...
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MCU Status Register – MCUSR The MCU Status Register provides information on which reset source caused an MCU Reset. Bit Read/Write Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and ...
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ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode. Table 8-4. Symbol 8.9 ...
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Watchdog Timer Control Register – WDTCR Bit Read/Write Initial Value • Bit 7 – WDIF: Watchdog Timeout Interrupt Flag This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config- ured for ...
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In safety level 1, WDE is overridden by WDRF in MCUSR. See MCUSR” on page 40 is set. To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure described above. This feature ensures multiple resets during ...
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The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will occur during execution of these functions. Assembly ...
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Safety Level 2 In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following ...
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If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATtiny25/45/85 ...
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Figure 10-1. I/O Pin Equivalent Schematic All registers and bit references in this section are written in general form. A lower case “x” repre- sents the numbering letter for the port, and a lower case “n” represents the bit number. ...
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Figure 10-2. General Digital I/O Note: 10.2.1 Configuring the Pin Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in Description for I/O-Ports” on page PORTxn bits at the PORTx I/O address, and the PINxn ...
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Switching Between Input and Output When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must ...
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Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...
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Assembly Code Example C Code Example unsigned char i; Note: 10.2.5 Digital Input Enable and Sleep Modes As shown in schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, ...
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Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...
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Note: Table 10-2 ure 10-5 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate ...
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MCU Control Register – MCUCR Bit Read/Write Initial Value • Bit 6 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are ...
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Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4 XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can not be ...
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OC0B: Output Compare Match output. The PB1 pin can serve as an external output for the Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1 set (one)) to serve this function. The OC0B pin ...
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Table 10-4 shown in Table 10-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: Table 10-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 7598H–AVR–07/09 and Table 10-5 relate ...
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Register Description for I/O-Ports 10.4.1 Port B Data Register – PORTB Bit Read/Write Initial Value 10.4.2 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 10.4.3 Port B Input Pins Address – PINB Bit Read/Write Initial Value ...
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MCU Control Register – MCUCR The External Interrupt Control Register A contains control bits for interrupt sense control. Bit Read/Write Initial Value • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The ...
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General Interrupt Flag Register – GIFR Bit Read/Write Initial Value • Bits 7, 4..0 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 and will always read as zero. • Bit 6 – INTF0: External Interrupt ...
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Timer/Counter0 with PWM Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate program execution timing (event man- agement) and wave generation. The main features are: • ...
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The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen- erator to generate a PWM or variable frequency output on ...
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Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...
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Figure 12-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...
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Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether ...
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The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 12.5.1 Compare Output Mode and Waveform Generation ...
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The timing diagram for the CTC mode is shown in increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 12-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be ...
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This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost. In fast PWM mode, the counter is ...
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Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.) A frequency (with 50% duty cycle) waveform output in fast PWM mode can ...
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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. In phase correct PWM mode, the compare unit allows ...
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Figure 12-8. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn TOVn Figure 12-9 Figure 12-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 12-10 mode and PWM mode, where OCR0A is TOP. Figure 12-10. Timer/Counter ...
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Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx OCFnx 12.8 8-bit Timer/Counter Register Description 12.8.1 Timer/Counter Control Register A – TCCR0A Bit Read/Write Initial Value • Bits 7:6 – ...
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Table 12-2. COM01 Note: Table 12-3 rect PWM mode. Table 12-3. COM0A1 Note: • Bits 5:4 – COM0B1:0: Compare Match Output B Mode These bits control the Output Compare pin (OC0B) behavior. If ...
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Table 12-2 mode. Table 12-5. COM01 Note: Table 12-3 rect PWM mode. Table 12-6. COM0A1 Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny25/45/85 ...
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Table 12-7. Mode Notes: 12.8.2 Timer/Counter Control Register B – TCCR0B Bit Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the ...
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A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved ...
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Output Compare Register B – OCR0B Bit Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, ...
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Bit 4– OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor- ...
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External Clock Source An external clock source applied to the T0 pin can be used as Timer/Counter clock (clk T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro- nized (sampled) signal is ...
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Figure 13-2. Prescaler for Timer/Counter0 Note: 13.2.1 General Timer/Counter Control Register – GTCCR Bit Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the ...
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Counter and Compare Units Figure 14-1 nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral clock (PCK) as the clock ...
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Figure 14-2. Timer/Counter 1 Synchronization Register Block Diagram. PCKE CK PCK SYNC MODE ASYNC MODE Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres- caler is operating on the fast 64 MHz (or 32 ...
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Figure 14-3. Timer/Counter1 Block Diagram Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and GTCCR. The interrupt enable/disable settings are found ...
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Timer/Counter1 Control Register - TCCR1 Bit $30 ($50) Read/Write Initial value • Bit 7- CTC1 : Clear Timer/Counter on Compare Match When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle ...
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Table 14-2. CS13 The Stop condition provides a Timer Enable/Disable function. 14.1.2 General Timer/Counter1 Control Register - GTCCR Bit $2C ($4C) Read/Write Initial value • Bit 6- PWM1B: Pulse Width Modulator B Enable When set (one) this bit enables PWM ...
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Bit 3- FOC1B: Force Output Compare Match 1B Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B) according to the values already set in COM1B1 and COM1B0. If COM1B1 and ...
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Timer/Counter1 Output Compare RegisterB - OCR1B Bit $2D ($4D) Read/Write Initial value The output compare register 8-bit read/write register. The Timer/Counter Output Compare Register B contains data to be continuously compared with Timer/Counter1. Actions on compare ...
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Bit 4– OCIE0A: Timer/Counter Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match A interrupt is enabled. The corresponding interrupt is ...
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In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C. Clearing the Timer/Counter1 with the bit CTC1 does not generate an ...
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Timer/Counter1 in PWM Mode When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C - OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the PB1(OC1A) and PB3(OC1B) pins and inverted outputs ...
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Figure 14-5. Effects of Unsynchronized OCR Latching During the time between the write and the latch operation, a read from OCR1A or OCR1B will read the contents of the temporary location. This means that the most recently written value always ...
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Resolution shows how many bit is required to express the value in the OCR1C register cal- culated by following equation Resolution Table 14-6. PWM Frequency ATtiny25/45/ log (OCR1C + 1). PWM 2 Timer/Counter1 Clock Prescale Select ...
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Dead Time Generator The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving external power control switches safely. The Dead Time Generator is a separate block that can be connected to Timer/Counter1 and it ...
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The length of the counting period is user adjustable by selecting the dead time prescaler setting in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register consists of two 4-bit fields, DT1xH and ...
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Timer/Counter1 Dead Time A - DT1A Bit $25 ($45) Read/Write Initial value The dead time value register 8-bit read/write register. The dead time delay of is adjusted by the dead time value register, DT1A. The register ...
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Universal Serial Interface – USI The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space ...
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This allows the counter to count the number of bits received or transmitted and generate an interrupt when the transfer is complete. Note that when an external clock source is selected the counter counts both clock edges. In this case ...
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Figure 16-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK The Three-wire mode timing is shown in Figure 16-3. At the top of the figure is a USCK cycle ref- erence. One bit is shifted into the USI Shift Register (USIDR) ...
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The code is size optimized using only eight instructions (+ ret). The code example assumes that the DO and USCK pins are enabled as output in the DDRE Register. The value stored in register r16 prior to the function is ...
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SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (+ ret). The code example assumes that the ...
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Figure 16-4. Two-wire Mode Operation, Simplified Diagram Figure 16 only the physical layer that is shown since the system operation is highly dependent of the communication scheme used. The main differences between the Master and Slave operation at ...
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Referring to the timing diagram (Figure 16-5.), a bus transfer involves the following steps: 1. The a start condition is generated by the Master by forcing the SDA low line while the SCL line is high (A). SDA can be ...
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Alternative USI Usage When the USI unit is not used for serial communication, it can be set alternative tasks due to its flexible design. 16.3.1 Half-duplex Asynchronous Data Transfer By utilizing the Shift Register in Three-wire ...
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USI Buffer Register – USIBR Bit Read/Write Initial Value The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com- pleted, and instead of accessing the USI Data Register (the Serial Register) ...
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The 4-bit counter increments by one for each clock generated either by the external clock edge detector Timer/Counter0 Compare Match software using USICLK or USITC strobe bits. The clock source depends of the setting of the ...
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Table 16-1. USIWM1 Note: • Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the ...
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Table 16-2 used for the Shift Register and the 4-bit counter. Table 16-2. USICS1 • Bit 1 – USICLK: Clock Strobe Writing a one to this bit location strobes the Shift Register to ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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This will reduce power consumption in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • ...
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Analog Comparator Multiplexed Input It is possible to select any of the ADC3..0 pins to replace the negative input to the Analog Com- parator. The ADC multiplexer is used to select this input, and consequently, the ADC must be ...
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Analog to Digital Converter 18.1 Features • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 260 µs Conversion Time • kSPS at Maximum Resolution • Four Multiplexed Single ...
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Figure 18-1. Analog to Digital Converter Block Schematic 18.2 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi- mation. The minimum value represents GND and the maximum value represents the voltage on V ...
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If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion circuitry can be measured directly as the result of the ...
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Figure 18-2. ADC Auto Trigger Logic Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly ...
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The ADC module contains a prescaler, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is ...
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Figure 18-5. ADC Timing Diagram, Single Conversion Cycle Number ADC Clock ADSC ADIF ADCH ADCL Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL Figure 18-7. ADC Timing Diagram, Free Running ...
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Table 18-1. Condition First conversion Normal conversions Auto Triggered conversions 18.5 Changing Channel or Reference Selection The MUX3..0 and REFS2..0 bits in the ADMUX Register are single buffered through a tempo- rary register to which the CPU has random access. ...
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ADC Voltage Reference The voltage reference for the ADC (V ended channels that exceed V either V version result after switching voltage reference source may be inaccurate, and the user is advised to discard this result. 18.6 ADC Noise ...
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Figure 18-8. Analog Input Circuitry 18.6.2 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. If conversion accuracy is critical, the noise level can be reduced by applying ...
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Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 18-10. Gain Error ...
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Figure 18-12. Differential Non-linearity (DNL) • Quantization Error: Due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB. ...
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V and V REF 124). The voltage on the positive pin must always be larger than the voltage on the negative pin or otherwise the voltage difference is saturated to zero. The result is presented in one-sided form, from ...
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The values described in Table 51 are typical values. However, due to the process variation the temperature sensor output voltage varies from one chip to another capable of achieving more accurate results the temperature measurement can be calibrated ...
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Bits 3:0 – MUX3:0: Analog Channel and Gain Selection Bits The value of these bits selects which combination of analog inputs are connected to the ADC. In case of differential input (ADC0 - ADC1 or ADC2 - ADC3), gain ...
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The first conversion after ADSC has been written after the ADC has been enabled ADSC is written at the same time as the ADC is enabled, will take 25 ADC clock cycles instead of the nor- mal 13. ...
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The ADC Data Register – ADCL and ADCH 18.7.7.1 ADLAR = 0 Bit Read/Write Initial Value 18.7.7.2 ADLAR = 1 Bit Read/Write Initial Value When an ADC conversion is complete, the result is found in these two registers. When ...
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Bit 5 – IPR: Input Polarity Mode The Input Polarity mode allows software selectable differential input pairs and full 10 bit ADC resolution, in the unipolar input mode, assuming a pre-determined input polarity. If the input polarity is not ...
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On-chip Debug System 19.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or ...
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-Up resistor on the dW/(RESET) line must be in the range of 10k However, the pull-up resistor ...
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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
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Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...
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Store Program Memory Control and Status Register – SPMCSR The Store Program Memory Control and Status Register contains the control bits needed to con- trol the Program memory operations. Bit Read/Write Initial Value • Bits 7..5 – Res: Reserved ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
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Flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if ...
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Table 21-2. LB Mode Notes: 21.2 Fuse Bytes The ATtiny25/45/85 has three Fuse bytes. the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if ...
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Table 21-4. Fuse High Byte BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes: Table 21-5. Fuse Low Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Notes: The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits ...
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Signature Bytes All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and High-voltage Programming mode, also when the device is locked. The three bytes reside in a separate ...
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Serial Downloading Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out- put). After RESET is ...
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To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following sequence is recommended (see four byte instruction formats in 1. Power-up sequence: Apply power between V tems, the programmer can not guarantee that SCK is held low ...
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Table 21-9. Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE Figure 21-2. Serial Programming Waveforms SERIAL DATA OUTPUT SERIAL CLOCK INPUT Table 21-10. Serial Programming Instruction Set Instruction Programming Enable Chip Erase Read Program Memory Load Program Memory Page ...
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Table 21-10. Serial Programming Instruction Set Instruction Load EEPROM Memory Page (page access) Write EEPROM Memory Page (page access) Read Lock bits Write Lock bits Read Signature Byte Write Fuse bits Write Fuse High bits Write Extended Fuse Bits Read ...
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Serial Programming Characteristics Figure 21-3. Serial Programming Timing Table 21-11. Serial Programming Characteristics, T Symbol 1/t CLCL t CLCL 1/t CLCL t CLCL 1/t CLCL t CLCL t SHSL t SLSH t OVSH t SHOX Note: 21.7 High-voltage Serial ...
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Figure 21-4. High-voltage Serial Programming Table 21-12. Pin Name Mapping Signal Name in High-voltage Serial Programming Mode SDI SII SDO SCI Table 21-13. High-voltage Serial Programming Characteristics T Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t ...
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High-voltage Serial Programming Algorithm Sequence To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the fol- lowing sequence is recommended (See instruction formats in 21.8.1 Enter High-voltage Serial Programming Mode The following algorithm puts the device ...
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Programming the Flash The Flash is organized in pages, see the program data is latched into a page buffer. This allows one page of program data to be pro- grammed simultaneously. The following procedure describes how to program the ...
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Programming the EEPROM The EEPROM is organized in pages, see EEPROM, the data is latched into a page buffer. This allows one page of data to be pro- grammed simultaneously. The programming algorithm for the EEPROM Data memory is ...
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Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 Instruction Instr.1/5 SDI 0_1000_0000_00 Chip Erase SII 0_0100_1100_00 SDO x_xxxx_xxxx_xx SDI 0_0001_0000_00 Load “Write Flash” SII 0_0100_1100_00 Command SDO x_xxxx_xxxx_xx SDI 0_ bbbb_bbbb _00 SII 0_0000_1100_00 SDO x_xxxx_xxxx_xx Load Flash Page ...
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Table 21-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued) Instruction Instr.1/5 SDI 0_bbbb_bbbb_00 Read EEPROM SII 0_0000_1100_00 Byte SDO x_xxxx_xxxx_xx SDI 0_0100_0100_00 Write Fuse Low SII 0_0100_1100_00 Bits SDO x_xxxx_xxxx_xx SDI 0_0100_0000_00 Write Fuse High SII 0_0100_1100_00 Bits SDO ...
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High-voltage Serial Programming Characteristics Figure 21-7. High-voltage Serial Programming Timing Table 21-17. High-voltage Serial Programming Characteristics T Symbol t SHSL t SLSH t IVSH t SHIX t SHOV t WLWH_PFB 7598H–AVR–07/ 5.0V ±10% (Unless otherwise ...
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Electrical Characteristics 22.1 Absolute Maximum Ratings* Operating Temperature.................................. -40°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...
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Table 22-1. DC Characteristics T Symbol Parameter Power Supply Current ( (7) Power-down mode Notes: 1. All DC Characteristics contained in this data sheet result from actual silicon characterization. 2. “Max” means the highest value where the pin ...
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External Clock Drive Table 22-2. Symbol 1/t CLCL t CLCL t CHCX t CLCX t CLCH t CHCL t CLCL Note: Figure 22-2. Maximum Frequency vs. V ATtiny25/45/85 152 (1) External Clock Drive . PRELIMINARY Parameter Clock Frequency Clock ...
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ADC Characteristics – Preliminary Data Table 22-3. ADC Characteristics, Single Ended Channels. -40°C - 125°C. Symbol Parameter Resolution Absolute accuracy (Including INL, DNL, quantization error, gain and offset error) Integral Non-linearity (INL) Differential Non-linearity (DNL) Gain Error Offset Error ...
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Calibrated RC Oscillator Accuracy Table 22-4. Factory Calibration User Calibration 23. Typical Characteristics The data contained in this section is extracted from preliminary silicon characterization and will be updated upon final characterization. The following charts show typical behavior. These ...
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Active Supply Current Figure 23-1. Active Supply Current vs. Frequency (0.1 - 1.0 MHz) 0.040 0.035 0.030 0.025 0.020 0.015 0.010 0.005 0.000 0 Figure 23-2. Active Supply Current vs. Frequency ( MHz ...
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Figure 23-3. Active Supply Current vs. V 0.25 0.2 0.15 0.1 0.05 Figure 23-4. Active Supply Current vs. V 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 ATtiny25/45/85 156 ACTIVE CURRENT ...
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Figure 23-5. Active Supply Current vs 1.5 23.2 Idle Supply Current Figure 23-6. Idle Supply Current vs. Frequency (0.1 - 1.0 MHz) 7598H–AVR–07/09 CC ACTIVE CURRENT ...
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Figure 23-7. Idle Supply Current vs. Frequency ( MHz) Figure 23-8. Idle Supply Current vs. V 0.25 0.2 0.15 0.1 0.05 ATtiny25/45/85 158 IDLE CURRENT vs . FREQUENCY 4 3.5 3 2.5 2 1.5 ...
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Figure 23-9. Idle Supply Current vs. V 0.6 0.5 0.4 0.3 0.2 0.1 0 Figure 23-10. Idle Supply Current vs 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 7598H–AVR–07/09 CC IDLE CURRENT ...
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Using the Power Reduction Register The tables and formulas below can be used to calculate the additional current consumption for the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules are controlled ...
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Power-Down Supply Current Figure 23-11. Power-Down Supply Current vs. V Figure 23-12. Power-Down Supply Current vs. V 7598H–AVR–07/09 P OWER-DOWN CURRENT WATCHDOG TIMER DISABLED 4 3.5 3 2.5 2 1.5 1 0.5 ...
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Pin Pull-up Figure 23-13. I/O Pin Pull-Up Resistor Current vs. Input Voltage ( Figure 23-14. I/O Pin Pull-Up Resistor Current vs. Input Voltage ( ...
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Figure 23-15. I/O Pin Pull-Up Resistor Current vs. Input Voltage (V 160 140 120 100 Figure 23-16. Reset Pull-Up Resistor Current vs. Reset Pin Voltage ( 7598H–AVR–07/09 ...
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Figure 23-17. Reset Pull-Up Resistor Current vs. Reset Pin Voltage ( Figure 23-18. Reset Pull-Up Resistor Current vs. Reset Pin Voltage (V 140 120 100 ATtiny25/45/85 164 RES ...
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Pin Driver Strength Figure 23-19. I/O Pin Source Current vs. Output Voltage ( Figure 23-20. I/O Pin Source Current vs. Output Voltage (V 1.2 0.8 0.6 0.4 0.2 7598H–AVR–07/09 I ...
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Figure 23-21. I/O Pin Source Current vs. Output Voltage (V 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 Figure 23-22. I/O Pin Sink Current vs. Output Voltage ( ATtiny25/45/85 166 ...
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Figure 23-23. I/O Pin Sink Current vs. Output Voltage (V 3.5 2.5 1.5 0.5 Figure 23-24. I/O Pin Sink Current vs. Output Voltage (V 5.1 4.9 4.8 4.7 4.6 4.5 4.4 4.3 7598H–AVR–07/09 I OUTP UT VOLTAGE vs ...
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Pin Thresholds and Hysteresis Figure 23-25. I/O Pin Input Threshold Voltage vs. V Figure 23-26. I/O Pin Input Threshold Voltage vs. V ATtiny25/45/85 168 I INP UT THRES HOLD VOLTAGE VIH, IO PIN READ ...
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Figure 23-27. I/O Pin Input Hysteresis vs. V Figure 23-28. Reset Input Threshold Voltage vs. V 7598H–AVR–07/09 I INP UT HYS TERES IS 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 V ...
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Figure 23-29. Reset Input Threshold Voltage vs. V 2.5 2 1.5 0.5 0 Figure 23-30. Reset Input Pin Hysteresis vs. V 0.25 0.2 0.15 0.1 0.05 ATtiny25/45/85 170 RES ET INP UT THRES HOLD VOLTAGE VIL, IO ...
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BOD Thresholds and Analog Comparator Offset Figure 23-31. BOD Thresholds vs. Temperature (BODLEVEL Is 4.3V) 4.4 4.35 4.3 4.25 4.2 4.15 4.1 4.05 Figure 23-32. BOD Thresholds vs. Temperature (BODLEVEL Is 2.7V) 2.8 2.75 2.7 2.65 2.6 2.55 2.5 ...
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Figure 23-33. BOD Thresholds vs. Temperature (BODLEVEL Is 1.8V) 1.9 1.85 1.8 1.75 1.7 1.65 1.6 23.8 Internal Oscillator Speed Figure 23-34. Watchdog Oscillator Frequency vs. V 0.118 0.116 0.114 0.112 0.11 0.108 0.106 0.104 0.102 ATtiny25/45/85 172 BOD THRES ...
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Figure 23-35. Watchdog Oscillator Frequency vs. Temperature 0.118 0.116 0.114 0.112 0.11 0.108 0.106 0.104 0.102 Figure 23-36. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature 8.4 8.3 8.2 8.1 8 7.9 7.8 7.7 7.6 7.5 7598H–AVR–07/09 WATCHDOG OS CILLATOR ...
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Figure 23-37. Calibrated 8 MHz RC Oscillator Frequency vs. V 8.4 8.3 8.2 8.1 8 7.9 7.8 7.7 7.6 7.5 Figure 23-38. Calibrated 8 MHz RC Oscillator Frequency vs. Osccal Value ATtiny25/45/85 174 ...
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Current Consumption of Peripheral Units Figure 23-39. Brownout Detector Current vs Figure 23-40. Analog Comparator Current vs. V 350 300 250 200 150 100 50 7598H–AVR–07/09 BROWNOUT DETECTOR CURRENT vs ...
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Current Consumption in Reset and Reset Pulse width Figure 23-41. Reset Supply Current vs. V 0.14 0.12 0.1 0.08 0.06 0.04 0.02 Figure 23-42. Reset Supply Current vs. V 2.5 2 1.5 1 0.5 0 ATtiny25/45/85 176 Reset Pull-up) ...
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Figure 23-43. Reset Pulse Width vs. V 2500 2000 1500 1000 500 23.11 Analog to Digital Converter Figure 23-44. Analog to Digital Converter Differential mode OFFSET vs 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -40 7598H–AVR–07/09 CC ...
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Figure 23-45. Analog to Digital Converter Single Endded mode OFFSET vs. V 2.5 2 1.5 1 0.5 0 Figure 23-46. Analog to Digital Converter Differential mode GAIN vs -1.2 -1.4 -1.6 -1.8 -2 -2.2 -2.4 -2.6 -2.8 -3 ...
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Figure 23-47. Analog to Digital Converter Single Endded mode GAIN vs. V -0.5 -1 -1.5 -2 -2.5 Figure 23-48. Analog to Digital Converter Differential mode DNL vs. V 1.2 1 0.8 0.6 0.4 0.2 0 7598H–AVR–07/09 Analog to Digital Converter ...
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Figure 23-49. Analog to Digital Converter Single Endded mode DNL vs. V 0.57 0.56 0.55 0.54 0.53 0.52 0.51 0.5 0.49 0.48 0.47 Figure 23-50. Analog to Digital Converter differential mode INL vs. V 1.8 1.6 1.4 1.2 1 0.8 ...
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Figure 23-51. Analog to Digital Converter Single Endded mode INL vs. V 0.72 0.7 0.68 0.66 0.64 0.62 0.6 0.58 7598H–AVR–07/09 Analog to Digital Converter - Integral Non Linearity INL Single Ended, Vcc = 4V, Vref = 4V -40 -30 ...
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Register Summary Address Name Bit 7 0x3F SREG I 0x3E SPH – 0x3D SPL SP7 0x3C Reserved 0x3B GIMSK – 0x3A GIFR – 0x39 TIMSK – 0x38 TIFR – 0x37 SPMCSR – 0x36 Reserved 0x35 MCUCR BODS 0x34 MCUSR ...
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Address Name Bit 7 0x08 ACSR ACD 0x07 ADMUX REFS1 0x06 ADCSRA ADEN 0x05 ADCH 0x04 ADCL 0x03 ADCSRB BIN 0x02 Reserved 0x01 Reserved 0x00 Reserved Notes: 1. For compatibility with future devices, reserved bits should be written to zero ...
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Instruction Set Summary Mnemonics Operands ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract ...
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Mnemonics Operands ROR Rd Rotate Right Through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set BCLR s Flag Clear BST Rr, b Bit Store from Register to T BLD Rd, b Bit load from ...
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Ordering Information Power Supply Speed (MHz) 2 2 Notes: 1. Green and ROHS packaging 2. Tape and Reel with Dry-pack delivery. 3. For Speed vs. V ,see Figure 22-2 ...
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Packaging Information 27.1 T5 7598H–AVR–07/09 ATtiny25/45/85 187 ...
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PC ATtiny25/45/85 188 7598H–AVR–07/09 ...
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Document Revision History 28.1 Revision 7598H - 07/09 1. Absolute Maximum Ratings updated 28.2 Revision 7598G - 03/08 1. Modified 2. Modified 3. Modified 4. Added 5. Modified 28.3 Revision 7598F - 11/07 1. Correction to ICC Active, 28.4 ...
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Errata The revision letter in this section refers to the revision of the ATtiny25/45/85 device. 29.1 ATtiny25, Revision known errata. Flash security improvements. 29.2 ATtiny45, Revision known errata. Flash security improvements. 29.3 ATtiny85, ...
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Table of Contents Features ..................................................................................................... 1 1 Pin Configurations ................................................................................... 2 2 Overview ................................................................................................... 2 3 About Code Examples ............................................................................. 5 4 AVR CPU Core .......................................................................................... 5 5 AVR ATtiny25/45/85 Memories ............................................................. 13 6 System Clock and Clock Options ...
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Power Management and Sleep Modes ................................................. 31 8 System Control and Reset .................................................................... 35 9 Interrupts ................................................................................................ 45 10 I/O Ports .................................................................................................. 46 11 External Interrupts ................................................................................. 58 12 8-bit Timer/Counter0 with PWM ............................................................ 61 ATtiny25/45/85 192 7.1 MCU ...
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Timer/Counter Prescaler ....................................................................... 78 14 Counter and Compare Units ................................................................. 81 15 Dead Time Generator ............................................................................. 93 16 Universal Serial Interface – USI ............................................................ 96 17 Analog Comparator ............................................................................. 108 18 Analog to Digital Converter ................................................................ 111 19 debugWIRE ...
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Self-Programming the Flash ............................................................... 130 21 Memory Programming ......................................................................... 134 22 Electrical Characteristics .................................................................... 150 23 Typical Characteristics ........................................................................ 154 ATtiny25/45/85 194 19.2 Overview ........................................................................................................128 19.3 Physical Interface ..........................................................................................128 19.4 Software Break Points ...................................................................................129 19.5 Limitations of debugWIRE .............................................................................129 ...
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Register Summary .............................................................................. 182 25 Instruction Set Summary .................................................................... 184 26 Ordering Information ........................................................................... 186 27 Packaging Information ........................................................................ 187 28 Document Revision History ................................................................ 189 29 Errata ..................................................................................................... 190 30 Table of Contents ................................................................................. 191 7598H–AVR–07/09 23.9 Current ...
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... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. International Atmel Asia Atmel Europe Unit 1-5 & ...