ATmega48PA Automotive Atmel Corporation, ATmega48PA Automotive Datasheet - Page 214

• Manufacturer Part Number: ATmega48PA Automotive
• Manufacturer: Atmel Corporation

22.3
22.3.1
22.3.2
214
Data Transfer and Frame Format
Atmel ATmega48PA/88PA/168PA [Preliminary]
Transferring Bits
START and STOP Conditions
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The
level of the data line must be stable when the clock line is high. The only exception to this rule
is for generating start and stop conditions.
Figure 22-2. Data Validity
The Master initiates and terminates a data transmission. The transmission is initiated when
the Master issues a START condition on the bus, and it is terminated when the Master issues
a STOP condition. Between a START and a STOP condition, the bus is considered busy, and
no other master should try to seize control of the bus. A special case occurs when a new
START condition is issued between a START and STOP condition. This is referred to as a
REPEATED START condition, and is used when the Master wishes to initiate a new transfer
without relinquishing control of the bus. After a REPEATED START, the bus is considered
busy until the next STOP. This is identical to the START behavior, and therefore START is
used to describe both START and REPEATED START for the remainder of this datasheet,
unless otherwise noted. As depicted below, START and STOP conditions are signalled by
changing the level of the SDA line when the SCL line is high.
Figure 22-3. START, REPEATED START and STOP conditions
SDA
SCL
START
SDA
SCL
Data Stable
STOP
Data Change
START
Data Stable
REPEATED START
STOP
9223B–AVR–09/11