CLC411AJE National Semiconductor, CLC411AJE Datasheet - Page 10

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CLC411AJE

Manufacturer Part Number
CLC411AJE
Description
IC OP AMP HI SPEED VIDEO 8-SOIC
Manufacturer
National Semiconductor
Datasheet

Specifications of CLC411AJE

Applications
Current Feedback
Number Of Circuits
1
-3db Bandwidth
200MHz
Slew Rate
2300 V/µs
Current - Supply
11mA
Current - Output / Channel
70mA
Mounting Type
Surface Mount
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*CLC411AJE

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graph as solid dots. The required voltage sources are +V
+12V, +V
reference voltages are applied, the range for VO is −3V to
+9V, and CMIR ranges from −1V to +7V. The difference
between the minimum and maximum voltages is constant,
i.e. 12V for VO, only the midpoint has been shifted, i.e. from
0V to +3V for VO.
Note that in this example the −V
bypassed to reduce high-frequency noise). The difference
between +V
can be applied to only one of the reference pins, not both. If
extended operation were needed in the negative direction,
Figure 4 may be used by changing the signs, and applying
the resultant negative voltage to the −V
mended that +V
negative shifts of input/output voltage range.
Printed Circuit Layout and Evaluation Board
Refer to application note OA-15, Frequent Faux Pas in
Applying Wideband Current Feedback Amplifiers, for board
CC
= +12V, −V
r
and −V
r
be used for positive shifts, and −V
r
is fixed by V
CC
= −12V. When these supply and
r
pin has been left open (or
z
. A level-shifting voltage
r
pin. It is recom-
r
r
for
=
10
layout guidelines and construction techniques. Two very im-
portant points to consider before creating a layout which are
found in the above application note are worth reiteration.
First the input and output pins are sensitive to parasitic
capacitances. These parasitic capacitances can cause
frequency-response peaking or sustained oscillation. To
minimize the adverse effect of parasitic capacitances, the
ground plane should be removed from those pins to a dis-
tance of at least 0.25% Second, leads should be kept as
short as possible in the finished layout. In particular, the
feedback resistor should have its shortest lead on the invert-
ing input side of the CLC411. The output is less sensitive to
parasitic capacitance and therefore can drive the longer of
the two feedback resistor connections. The evaluation board
available for the CLC411 (part #730013 for through hold
packages, 730027 for SO8) may be used as a reference for
proper board layout. Application schematics for this evalua-
tion board are in the product accessories section of the
National databook.

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