CLC412AJE National Semiconductor, CLC412AJE Datasheet - Page 13

• Manufacturer Part Number: CLC412AJE
• Description: IC OP AMP VIDEO DUAL 8-SOIC
• Manufacturer: National Semiconductor

Specifications of CLC412AJE

• Applications: Current Feedback
• Number Of Circuits: 2
• -3db Bandwidth: 250MHz
• Slew Rate: 1300 V/µs
• Current - Supply: 10.2mA
• Current - Output / Channel: 70mA
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC412AJE

2V step. Also, the amplifier is virtually free of any long term
thermal tail effects at low gains as shown in the Typical
Performance plot labeled “Long Term Settling Time.”
When measuring settling time, a solid ground plane should
be used in order to reduce ground inductance which can
cause common-ground-impedance coupling. Power supply
and ground trace parasitic capacitances and the load ca-
pacitance will also affect settling time.
Placing a series resistor (R
mended for optimal settling time performance when driving a
capacitive load. The Typical Performance plot labeled “R
and Settling Time vs. Capacitive Load” provides a means for
selecting a value of R
also shows the resulting settling time to 0.05% and 0.01%.
DC & Noise Performance
A current-feedback amplifier’s input stage does not have
equal nor correlated bias currents, therefore they cannot be
canceled and each contributes to the total DC offset voltage
at the output by the following equation:
The input resistor R
non-inverting input back toward the source. For inverting
DC-offset calculations, the source resistance seen by the
input resistor R
lation as a part of the non-inverting gain equation. Applica-
tion note OA-7 gives several circuits for DC offset correction.
The noise currents for the inverting and non-inverting inputs
are graphed in the Typical Performance plot labeled “Equiva-
lent Input Noise”. A more complete discussion of amplifier
input-referred noise and external resistor noise contribution
can be found in OA-12.
Differential Gain & Phase
The CLC412 can drive multiple video loads with very low
differential gain and phase errors. The Typical Performance
plots labeled “Differential Gain vs. Frequency” and “Differen-
tial Phase vs. Frequency” show performance for loads from
1 to 4. The Electrical Characteristics table also specifies
guaranteed performance for one 150 load at 4.43MHz. For
NTSC video, the guaranteed performance specifications
also apply. Application note OA-08, “Differential Gain and
Phase for Composite Video Systems”, describes in detail the
techniques used to measure differential gain and phase.
I/O Voltage & Output Current
The usable common-mode input voltage range (CMIR) of
the CLC412 specified in the Electrical Characteristics table
of the data sheet shows a range of
this range will cause the input stage to saturate and clip the
output signal.
The output voltage range is determined by the load resistor
and the choice of power supplies. With
output driver will typically drive +3.1/-2.7 volts into a load
resistance of 100 . Increasing the supply voltages will
change the common-mode input and output voltage swings
while at the same time increase the internal junction tem-
perature. The output voltage for different load resistors can
be determined from the data sheet plots labeled “Frequency
Response vs. Load (R
Frequency”.
Applications Circuits
Single-to-Differential Line Driver
g
must be included in the output offset calcu-
in
s
L
for a given capacitive load. The plot
)” and “Maximum Output Swing vs.
is the resistance looking from the
s
) at the output pin is recom-
±
±
2.2 volts. Exceeding
5 volts the class A/B
s
13
The CLC412’s well matched AC channel-response allows a
single-ended input to be transformed to highly matched
push-pull driver. From a 1V single-ended input the circuit of
Figure 4 produces 1V differential signal between the two
outputs. For larger signals the input voltage divider (R
2R
achieve the same performance when driving a matched
load, see Figure 3
Differential Line Receiver. Figure 5 and Figure 6 show two
different implementations of an instrumentation amplifier
which convert differential signals to single-ended. Figure 6
allows CMRR adjustment through R
2
) is necessary to limit the input voltage on channel 2. To
FIGURE 4.
FIGURE 5.
2
.
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