CLC5623IN National Semiconductor, CLC5623IN Datasheet - Page 12

• Manufacturer Part Number: CLC5623IN
• Description: IC AMP VIDEO TRIPLE 14-DIP
• Manufacturer: National Semiconductor

Specifications of CLC5623IN

• Applications: Current Feedback
• Number Of Circuits: 3
• -3db Bandwidth: 148MHz
• Slew Rate: 370 V/µs
• Current - Supply: 3.2mA
• Current - Output / Channel: 130mA
• Mounting Type: Through Hole
• Package / Case: 14-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *CLC5623IN

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Application Division
The denominator of Equation 1 is approximately equal to 1 at
low frequencies. Near the −3dB corner frequency, the
interaction between R
performance. The value of the feedback resistor has a large
affect on the circuits performance. Increasing R
following affects:
Refer to the Feedback Resistor Selection section for more
details on selecting a feedback resistor value.
CLC5623 Design Information
Single Supply Operation (V
The specifications given in the operation are measured with
a common mode voltage (V
around which the inputs are applied and the output voltages
are specified.
Operating from a single +5V supply, the Common Mode
Input Range (CMIR) of the CLC5623 is typically +0.8V to
+4.2V. The typical output range with R
+4.0V.
For single supply DC coupled operation, keep input signal
levels above 0.8V DC. For input signals that drop below 0.8V
DC, AC coupling and level shifting the signal are
recommended. The non-inverting and inverting configura-
tions for both input conditions are illustrated in the following
2 sections.
DC Coupled Single Supply Operation
Figure 1 and Figure 2 show the recommended non-inverting
and inverting configurations for input signals that remain
above 0.8V DC.
• Decreases loop gain
• Decreases bandwidth
• Reduces gain peaking
• Lowers pulse response overshoot
• Affects frequency response phase linearity
V
Note: R
to V
consumption and maximum
output swing.
in
cm
for minimum power
FIGURE 1. Non-Inverting Configuration
t
, R
V
L
and R
cm
R
t
g
are tied
V
cm
f
R
5
6
and Z(j ) dominates the circuit
g
CM
CLC5623
+
-
CC
V
) of 2.5V. V
1/3
CC
= +5V, V
11
4
(Continued)
6.8 F
0.1 F
V
V
L
+
R
in
o
= 100
f
EE
7
CM
A
= GND)
is the voltage
v
V
is +1.0V to
DS015004-39
f
1
cm
has the
R
R
R
L
V
g
f
o
12
V
AC Coupled Single Supply Operation
and show possible non-inverting and inverting configurations
for input signals that go below 0.8V DC. The input is AC
coupled to prevent the need for level shifting the input signal
at the source. The resistive voltage divider biases the
non-inverting input to V
low frequency cutoff
V
low frequency cutoff
V
o
o
in
Note: R
for non-inverting input.
R
to V
consumption and maximum
output swing.
FIGURE 3. AC Coupled Non-Inverting Configuration
V
b
, R
V
FIGURE 4. AC Coupled Inverting Configuration
in
V
cm
in
in
V
V
L
V
and R
for minimum power
cm
cm
1
b
in
, provides DC bias
C
R
R
R
c
FIGURE 2. Inverting Configuration
R
R
g
f
t
t
g
f
R
are tied
R
b
V
V
V
2.5
V
C
R
2.5
2
in
CC
o
g
CC
2
c
g
2 R C
2 R C
A
CC
1
v
in c
5
6
1
g c
R
R
R
R
÷ 2 = 2.5V (For V
CLC5623
-
-
+
+
, where: R
V
R
R
1/3
CC
g
11
4
f
R
C
5
6
5
6
g
CLC5623
CLC5623
6.8 F
0.1 F
-
+
+
-
Select R
desired R
V
V
in
+
R
1/3
1/3
CC
CC
4
11
4
11
f
7
R
2
6.8 F
0.1 F
6.8 F
0.1 F
CC
+
+
R
R
f
f
t
7
7
V
= +5V).
to yield
in
R
cm
= R
R
DS015004-42
DS015004-40
L
R
DS015004-41
V
t
source
|| R
o
V
V
o
o
g