AD9648 Analog Devices, AD9648 Datasheet - Page 15

• Manufacturer Part Number: AD9648
• Description: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9648

• Resolution (bits): 14bit
• # Chan: 2
• Sample Rate: 125MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p,2 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
ADC Power Supplies
10, 19, 28, 37
49, 50, 53, 54,
59, 60, 63, 64
4, 5, 6, 7
0
ADC Analog
51
52
62
61
55
56
58
57
1
2
Digital Input
3
Digital Outputs
9
8
12
11
Mnemonic
DRVDD
AVDD
NC
AGND,
Exposed Pad
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
CLK+
CLK−
SYNC
D0+ (LSB)
D0− (LSB)
D1+
D1−
D0– (LSB)
D0+ (LSB)
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2.
THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
DRVDD
Type
Supply
Supply
Ground
Input
Input
Input
Input
Input/Output
Input
Input/Output
Output
Input
Input
Input
Output
Output
Output
Output
SYNC
CLK+
CLK–
D1–
D1+
D2–
D2+
D3–
D3+
NC
NC
NC
NC
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View)
Description
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
No Connect. Do not connect to these pins.
The exposed thermal pad on the bottom of the package provides the analog ground for
the part. This exposed pad must be connected to ground for proper operation.
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Voltage Reference Input/Output.
Reference Mode Selection.
External Reference Bias Resistor.
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
Digital Synchronization Pin. Slave mode only.
Channel A/Channel B LVDS Output Data 0—True.
Channel A/Channel B LVDS Output Data 0—Complement.
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
PIN 1
INDICATOR
INTERLEAVED PARALLEL LVDS
(Not to Scale)
Rev. 0 | Page 15 of 44
AD9648
TOP VIEW
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PDWN
OEB
CSB
SCLK/DFS
SDIO/DCS
OR+
OR–
D13+ (MSB)
D13– (MSB)
D12+
D12–
DRVDD
D11+
D11–
D10+
D10–
AD9648