AD9641 Analog Devices, AD9641 Datasheet - Page 31

• Manufacturer Part Number: AD9641
• Description: 14-Bit, 80 MSPS/155 MSPS, 1.8 V Serial Output Analog-to-Digital Converter (ADC)
• Manufacturer: Analog Devices

Specifications of AD9641

• Resolution (bits): 14bit
• # Chan: 1
• Sample Rate: 80MSPS
• Interface: Ser
• Analog Input Type: Diff-Bip
• Ain Range: 1.75 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Data Sheet
Addr
(Hex)
0x1E
0x1F
0x20
0x21
0x24
0x25
0x3A
JESD204A Configuration Registers
0x60
0x61
0x62
0x63
0x64
0x65
0x66
0x6E
Register
Name
User Test
Pattern 3 MSB
User Test
Pattern 4 LSB
User Test
Pattern 4 MSB
PLL control
BIST
signature LSB
BIST
signature
MSB
Sync control
JESD204A
Link Control
Register 1
JESD204A
Link Control
Register 2
JESD204A
Link Control
Register 3
JESD204A
Link Control
Register 4
JESD204A
device
identification
number
(DID)
JESD204A
bank
identification
number
(BID)
JESD204A
lane
identification
number
(LID)
JESD204A
scrambler
(SCR) and
lane (L)
configuration
Bit 7
(MSB)
Open
Open
Disable
CHKSUM
Open
Open
Enable
serial
scrambler
mode (SCR)
10 = DSYNC active mode
11 = DSYNC pin disabled
Open
Local DSYNC mode
00 = individual mode
01 = global mode
Bit 6
Open
Serial tail
bit enable
Open
Open
Open
Open
Open
Bit 5
Open
Serial test
sample
enable
DSYNC
pin input
inverted
00 = 16-bit data injected
01 = 10-bit data injected
Open
Open
Open
at sample input to the
JESD204A serial device identification (DID) number
Open
Link test generation
at output of 8b/10b
Initial lane assignment sequence repeat count
input selection
10 = reserved
11 = reserved
encoder
link
User Test Pattern 3, Bits[15:8]
User Test Pattern 4, Bits[15:8]
User Test Pattern 4, Bits[7:0]
Bit 4
Open
Serial lane
synchroni-
zation
enable
CMOS
DSYNC
input
0 = LVDS
1 = CMOS
Open
Open
BIST signature, Bits[15:8]
BIST signature, Bits[7:0]
Open
Rev. B | Page 31 of 36
JESD204A serial lane identification (LID) number
Bit 3
Open
Open
Open
Open
PLL low
encode
rate enable
Serial lane alignment
JESD204A serial bank identification (BID) number
sequence mode
00 = disabled
01 = enabled
11 = always on
10 = reserved
test mode
Bit 2
Bypass
8b/10b
encoding
Open
Clock
divider
next sync
only
101 = user test pattern data continuous
Open
110 = user test pattern data single
001 = alternating checkerboard
100 = PN sequence, short
011 = PN sequence, long
Link test generation mode
000 = normal operation
010 = 1/0 word toggle
111 = ramp output
Bit 1
Clock
divider
sync
enable
Frame
alignment
character
insertion
disable
Invert
transmit
bits
Open
Open
Bit 0
(LSB)
Master sync
buffer
enable
Serial
transmit link
power- down
Mirror serial
output bits
Serial lane
control
0 = one lane
per link
(L = 1)
1 = reserved
Open
0x00
0x00
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x80
AD9641
Default
Notes/
Comments
Bit 3 must
be enabled
if the ADC
clock rate is
<60 MHz.
Read only.
Read only.