AD6657 Analog Devices, AD6657 Datasheet - Page 2

• Manufacturer Part Number: AD6657
• Description: Quad IF Receiver
• Manufacturer: Analog Devices

AD6657
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
Absolute Maximum Ratings............................................................ 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 15
Theory of Operation ...................................................................... 16
REVISION HISTORY
8/11—Rev. A to Rev. B
Changes to Logic Input/Output (SDIO) Parameter Note,
Table 3 ................................................................................................ 6
Added Wake-Up Time (from Standby) Parameter, Table 4 and
Wake-Up Time (from Power Down) Parameter, Table 4 ............ 7
Changes to Figure 2.......................................................................... 8
Changes to Table 11........................................................................ 21
Updated Outline Dimensions ....................................................... 31
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
ADC Architecture ...................................................................... 16
Analog Input Considerations.................................................... 16
Clock Input Considerations ...................................................... 18
Rev. B | Page 2 of 32
Noise Shaping Requantizer (NSR) ............................................... 22
Built-In Self-Test (BIST) and Output Test .................................. 24
Serial Port Interface (SPI).............................................................. 25
Memory Map .................................................................................. 26
Applications Information .............................................................. 30
Outline Dimensions ....................................................................... 31
7/10—Rev. 0 to Rev. A
Changes to ADC Architecture Section........................................ 16
Changes to Figure 34 and Figure 35............................................. 18
Changes to Timing Section and Data Clock Output (DCO)
Section.............................................................................................. 21
Changes to 22% BW Mode (>40 MHz @ 184.32 MSPS) Section
and 33% BW Mode (>60 MHz @ 184.32 MSPS) Section ......... 22
Changed 0x0C to 0x79, Address 0x01, Table 13......................... 27
Changed DCO Output Delay (Global) to DCO Output Delay
(Local), Address 0x17, Table 13.................................................... 28
Changes to Design Guidelines Section........................................ 30
10/09—Revision 0: Initial Version
Power Dissipation and Standby Mode .................................... 20
Channel/Chip Synchronization................................................ 20
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 21
22% BW Mode (>40 MHz @ 184.32 MSPS)........................... 22
33% BW Mode (>60 MHz @ 184.32 MSPS)........................... 22
MODE Pin................................................................................... 23
Built-In Self-Test (BIST)............................................................ 24
Output Test Modes..................................................................... 24
Configuration Using the SPI..................................................... 25
Hardware Interface..................................................................... 25
Reading the Memory Map Register Table............................... 26
Memory Map Register Table..................................................... 27
Memory Map Register Descriptions........................................ 29
Design Guidelines ...................................................................... 30
Ordering Guide .......................................................................... 31
Data Sheet