AD7170 Analog Devices, AD7170 Datasheet - Page 7

• Manufacturer Part Number: AD7170
• Description: 12-Bit Low Power ??? ADC
• Manufacturer: Analog Devices

Specifications of AD7170

• Resolution (bits): 12bit
• # Chan: 1
• Interface: Ser,SPI
• Analog Input Type: Diff-Bip,Diff-Uni
• Ain Range: 2 V p-p
• Adc Architecture: Sigma-Delta
• Pkg Type: CSP

Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
SCLK
DOUT/RDY
AIN(+)
AIN(−)
REFIN(+)
REFIN(−)
GND
V
PDRST
NC
EPAD
DD
Description
Serial Clock Input. This serial clock input is for data transfers from the ADC. The SCLK has a Schmitt-triggered
input. The serial clock can be continuous with all data transmitted in a constant train of pulses. Alternatively, it
can be a noncontinuous clock with the information being transmitted from the ADC in smaller batches of data.
Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose. DOUT/RDY operates as a data ready
pin, going low to indicate the completion of a conversion. In addition, it functions as a serial data output pin to
access the data register of the ADC. Eight status bits accompany each data read. See
The DOUT/
the data is not read after the conversion, the pin goes high before the next update occurs.
Analog Input. AIN(+) is the positive terminal of the differential analog input pair AIN(+)/AIN(−).
Analog Input. AIN(−) is the negative terminal of the differential analog input pair AIN(+)/AIN(−).
Positive Reference Input. An external reference can be applied between REFIN(+) and REFIN(–). The nominal
reference voltage (REFIN(+) – REFIN(−)) is 5 V, but the part can function with a reference of 0.5 V to V
Negative Reference Input.
Ground Reference Point.
Supply Voltage, 2.7 V to 5.25 V.
Power-Down/Reset. When this pin is low, the ADC is placed in power-down mode. All the logic on the chip is
reset, and the DOUT/RDY pin is tristated. When PDRST is high, the ADC is taken out of power-down mode. The
on-chip clock powers up and settles, and the ADC continuously converts. The internal clock requires 1 ms
approximately to power up.
This pin should be connected to GND for correct operation.
Connect the exposed pad to ground.
RDY falling edge can be used as an interrupt to a processor, indicating that new data is available. If
DOUT/RDY
NOTES
1. NC = NO CONNECT.
2. CONNECT EXPOSED PAD TO GROUND.
REFIN(+)
AIN(+)
AIN(–)
SCLK
Figure 5. Pin Configuration
1
2
3
4
5
Rev. A | Page 7 of 16
(Not to Scale)
AD7170
TOP VIEW
10 NC
9
8
7
6
PDRST
V
GND
REFIN(–)
DD
Figure 13
for further details.
DD
AD7170
.