AD7682 Analog Devices, AD7682 Datasheet
AD7682
Specifications of AD7682
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AD7682 Summary of contents
Page 1
... V or 4.096 V) and buffer; a temperature sensor; a selectable one-pole filter; and a sequencer that is useful when channels are continuously scanned in order. The AD7682/AD7689 use a simple SPI interface for writing to the configuration register and receiving conversion results. The SPI interface uses a separate supply, VIO, which is set to the host logic level ...
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... General Timing with a Busy Indicator .................................... 27 Channel Sequencer .................................................................... 28 Read/Write Spanning Conversion Without a Busy Indicator ....................................................................................................... 29 Read/Write Spanning Conversion with a Busy Indicator..... 30 Application Hints ........................................................................... 31 Layout .......................................................................................... 31 Evaluating AD7682/AD7689 Performance ............................ 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 Changes to Figure 6, Figure 9, and Figure 10 ............................. 11 Changes to Figure 22...................................................................... 13 Changes to Overview Section and Converter Operation Section.............................................................................................. 15 Changes to Table 8 ...
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... Added Channel Sequencer Section and Figure 39 .....................27 Changes to Read/Write Spanning Conversion Without a Busy Indicator Section and Figure 41 ....................................................28 Changes to Read/Write Spanning Conversion with a Busy Indicator and Figure 43 ..................................................................29 Changes to Evaluating AD7682/AD7689 Performance Section ..............................................................................................30 Added Exposed Pad Notation to Outline Dimensions ..............31 Changes to Ordering Guide...........................................................31 5/08—Revision 0: Initial Version Rev ...
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... V 90 REF = 4.096 V, 89 REF = 2 REF = REF = 5 V, 30.5 REF = 4.096 V 88 REF = 2 REF Rev Page Data Sheet , unless otherwise noted. MAX AD7682B/AD7689B Min Typ Max REF /2 − REF REF + 0.1 −0 0.1 REF −0 − 0. ...
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... All specifications expressed in decibels are referred to a full-scale input FSR and tested with an input signal at 0.5 dB below full scale, unless otherwise specified. AD7689A Min Typ Max Min −97 105 −120 1.7 0.425 2.5 Rev Page AD7682/AD7689 AD7682B/AD7689B Typ Max Unit −100 dB 110 dB −125 dB 1.7 MHz 0.425 MHz 2 ...
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... AD7682/AD7689 VDD = 2 5.5 V, VIO = 1 VDD, V Table 3. Parameter Conditions/Comments INTERNAL REFERENCE REF Output Voltage 2 25°C 4.096 V, @ 25°C 1 REFIN Output Voltage 2 25°C 4.096 V, @ 25°C REF Output Current Temperature Drift Line Regulation VDD = 5 V ± 5% Long-Term Drift 1000 hours ...
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... CNVH SCK DSDO t 11 SCKL t 11 SCKH t 4 HSDO t DSDO DIS t 10 CLSCK t 5 SDIN t 5 HDIN Rev Page AD7682/AD7689 Typ Max Unit 2.2 μs μs μs 1.2 μ ...
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... AD7682/AD7689 VDD = 2 4.5 V, VIO = 1 VDD, all specifications T Table 5. 1 Parameter Conversion Time: CNV Rising Edge to Data Available Acquisition Time Time Between Conversions Data Write/Read During Conversion CNV Pulse Width SCK Period SCK Low Time SCK High Time SCK Falling Edge to Data Remains Valid ...
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... This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev Page AD7682/AD7689 ...
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... REF pin, as described in the REF pin description. P Power Supply Ground. AI AD7682: no connection. AD7689: Analog Input Channel 4. AI AD7682: Analog Input Channel 2. AD7689: Analog Input Channel 5. AI AD7682: no connection. AD7689: Analog Input Channel 6. AI AD7682: Analog Input Channel 3. AD7689: Analog Input Channel 7. ...
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... V, 2 V). AI Analog Input Channel 0. AI AD7682: no connection. AD7689: Analog Input Channel 1. AI AD7682: Analog Input Channel 1. AD7689: Analog Input Channel 2. AI AD7682: no connection. AD7689: Analog Input Channel 3. NC The exposed pad is not connected internally. For increased reliability of the solder joints recommended that the pad be soldered to the system ground plane ...
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... AD7682/AD7689 TYPICAL PERFORMANCE CHARACTERISTICS VDD = VIO = 2 VDD, unless otherwise noted. REF 1.5 INL MAX = +0.34 LSB INL MIN = –0.44 LSB 1.0 0.5 0 –0.5 –1.0 –1.5 0 16,384 32,768 CODES Figure 6. Integral Nonlinearity vs. Code, V 200k 180k 160k 135,326 140k 124,689 120k 100k ...
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... VDD = 5V 125 65 85 105 Rev Page AD7682/AD7689 100 VDD = 5V, –0.5dB REF VDD = 5V, –10dB REF V = VDD = 2.5V, –0.5dB REF VDD = 2.5V, –10dB REF 100 150 FREQUENCY (kHz) Figure 15 ...
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... AD7682/AD7689 –60 –70 –80 –90 –100 V REF –110 V REF V REF V REF –120 0 50 100 FREQUENCY (kHz) Figure 18. THD vs. Frequency 20kHz VDD = 5V REF VDD = 2.5V REF –10 –8 –6 –4 INPUT LEVEL (dB) Figure 19. SNR vs. Input Level ...
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... REF V where Max ) = maximum V REF V ( Min ) = minimum V REF V (25° 25°C. REF REF T = +85°C. MAX T = –40°C. MIN Rev Page AD7682/AD7689 ) measured REF . It is expressed in ppm/° Max – Min ) REF REF × ° × ...
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... The AD7682/AD7689 provide the user with an on-chip track- and-hold and do not exhibit pipeline delay or latency. The AD7682/AD7689 are specified from 2 5.5 V and can be interfaced to any 1 digital logic family. They are housed in a 20-lead × LFCSP that combines space savings and allows flexible configurations ...
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... INx− /2), the data outputs are REF twos complement. The ideal transfer characteristic for the AD7682/AD7689 is shown in Figure 25 and for both unipolar and bipolar ranges with the internal 4.096 V reference. Table 8. Output Codes and Ideal Input Voltages ...
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... AD7682/AD7689 TYPICAL CONNECTION DIAGRAMS REF ADA4841 REF ADA4841 REF NOTES 1. INTERNAL REFERENCE SHOWN. SEE VOLTAGE REFERENCE OUTPUT/INPUT SECTION FOR REFERENCE SELECTION USUALLY A 10µF CERAMIC CAPACITOR (X5R). REF 3. SEE THE DRIVER AMPLIFIER CHOICE SECTION FOR ADDITIONAL RECOMMENDED AMPLIFIERS. ...
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... ANALOG INPUTS Input Structure Figure 28 shows an equivalent circuit of the input structure of the AD7682/AD7689. The two diodes, D1 and D2, provide ESD protection for the analog inputs, IN[7:0] and COM. Care must be taken to ensure that the analog input signal does not exceed the supply rails by more than 0.3 V because this causes the diodes to become forward biased and to start conducting current ...
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... Sequencer section for further details of the sequencer operation. Source Resistance When the source impedance of the driving circuit is low, the AD7682/AD7689 can be driven directly. Large source imped- ances significantly affect the ac performance, especially THD. The dc performances are less sensitive to the input impedance. ...
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... AD7682/AD7689 GND pin. The internal reference is temperature-compensated to within 10 mV. The reference is trimmed to provide a typical drift of ±10 ppm/°C. Connect the AD7682/AD7689 as shown in Figure 31 for either a 2 4.096 V internal reference. Rev Page AD7682/AD7689 10µF ...
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... AD8031 or the AD8605. The placement of the reference decoupling capacitor is also impor- tant to the performance of the AD7682/AD7689, as explained in the Layout section. Mount the decoupling capacitor on the same side as the ADC at the REF pin with a thick PCB trace. The GND should also connect to the reference decoupling capacitor with the shortest distance and to the analog ground plane with several vias ...
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... VIO allows direct interface with any logic between 1.8 V and VDD. To reduce the supplies needed, the VIO and VDD pins can be tied together. The AD7682/AD7689 are independent of power supply sequencing between VIO and VDD. Additionally very insensitive to power supply varia- tions over a wide frequency range, as shown in Figure 34 ...
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... DATA CONV conversion results may be corrupted. The user should configure the AD7682/AD7689 and initiate the busy indicator (if desired also possible to corrupt the sample by having prior to t DATA SCK or DIN transitions near the sampling instant. Therefore, it ...
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... CFG register. Note that, at power-up, the CFG register is undefined and two dummy conversions are required to update the register. To preload the CFG register with a factory setting, hold DIN high for two conversions. Thus CFG[13:0] = 0x3FFF. This sets the AD7682/AD7689 for the following ...
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... A TOTAL OF 16 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 30 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 37. General Interface Timing for the AD7682/AD7689 Without a Busy Indicator When CNV is brought low after EOC, SDO is driven from high impedance to the MSB. Falling SCK edges clock out bits starting with MSB − ...
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... A TOTAL OF 17 SCK FALLING EDGES ARE REQUIRED TO RETURN SDO TO HIGH-Z. IF CFG READBACK IS ENABLED, A TOTAL OF 31 SCK FALLING EDGES IS REQUIRED TO RETURN SDO TO HIGH-Z. Figure 38. General Interface Timing for the AD7682/AD7689 With a Busy Indicator good example of this occurs when an SPI host sends 16 SCKs because these are usually limited to 8-bit or 16-bit bursts ...
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... AD7682/AD7689 CHANNEL SEQUENCER The AD7682/AD7689 include a channel sequencer useful for scanning channels in a repeated fashion. Channels are scanned as singles or pairs, with or without the temperature sensor, after the last channel is sequenced. The sequencer starts with IN0 and finishes with IN[7:0] set in CFG[9:7]. For paired channels, the channels are paired depend- ing on the last channel set in CFG[9:7] ...
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... SCK FALLING EDGES = LSB OF CONVERSION RESULTS. 29 SCK FALLING EDGES = LSB OF CONFIGURATION REGISTER. ON THE 16TH OR 30TH SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. Figure 41. Serial Interface Timing for the AD7682/AD7689 Without a Busy Indicator CNV low after t The host also must enable the MSB of the CFG register at this time (if necessary) to begin the CFG update ...
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... ON THE 17TH OR 31st SCK FALLING EDGE, SDO IS DRIVEN TO HIGH IMPENDANCE. OTHERWISE, THE LSB REMAINS ACTIVE UNTIL THE BUSY INDICATOR IS DRIVEN LOW. Figure 43. Serial Interface Timing for the AD7682/AD7689 with a Busy Indicator the CFG update. While CNV is low, both a CFG update and a data readback take place ...
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... The pinout of the AD7682/AD7689, with all its analog signals on the left side and all its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7682/AD7689 is used as a shield ...
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... LSB max AD7689ACPZRL7 ±6 LSB max AD7689BCPZ ±2 LSB max AD7689BCPZRL7 ±2 LSB max EVAL-AD7682EDZ EVAL-AD7689EDZ EVAL-CED1Z RoHS Compliant Part. 2 The EVAL-CED1Z controller board allows control and communicate with all Analog Devices evaluation boards whose model numbers end in ED. ...