AD7999 Analog Devices, AD7999 Datasheet - Page 20

• Manufacturer Part Number: AD7999
• Description: 4-Channel, 8-Bit ADC with I2C Compatible Interface in 8-Lead SOT-23
• Manufacturer: Analog Devices

Specifications of AD7999

• Resolution (bits): 8bit
• # Chan: 4
• Sample Rate: 140kSPS
• Interface: I²C/Ser 2-Wire
• Analog Input Type: SE-Uni
• Ain Range: (Vref) p-p,Uni (Vref),Uni Vdd
• Adc Architecture: SAR
• Pkg Type: SOT

AD7991/AD7995/AD7999
INTERNAL REGISTER STRUCTURE
CONFIGURATION REGISTER
The configuration register is an 8-bit write-only register that is used to set the operating modes of the AD7991/AD7995/AD7999. The bit
functions are outlined in Table 10. A single-byte write is necessary when writing to the configuration register. D7 is the MSB. When the
master writes to the AD7991/AD7995/AD7999, the first byte is written to the configuration register.
Table 9. Configuration Register Bit Map and Default Settings at Power-Up
D7
CH3
1
Table 10. Bit Function Descriptions
Bit
D7 to D4
D3
D2
D1
D0
Table 11. Channel Selection
D7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
The AD7991/AD7995/AD7999 converts on the selected channel in the sequence in ascending order, starting with the lowest channel in the sequence.
CH2
D6
1
D6
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Mnemonic
REF_SEL
FLTR
Bit trial delay
Sample delay
CH3 to CH0
D5
CH1
1
D5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Comment
These four channel address bits select the analog input channel(s) to be converted. If a channel address bit
(Bit D7 to Bit D4) is set to 1, a channel is selected for conversion. If more than one channel bit is set to 1, the
AD7991/AD7995/AD7999 sequence through the selected channels, starting with the lowest channel. All
unused channels should be set to 0. Table 11 shows how these four channel address bits are decoded. Prior
to the device initiating a conversion, the channel(s) must be selected in the configuration register.
This bit allows the user to select the supply voltage as the reference or choose to use an external reference. If
this bit is 0, the supply is used as the reference, and the device acts as a 4-channel input part. If this bit is set
to 1, an external reference must be used and applied to the V
input part.
The value written to this bit of the control register determines whether the filtering on SDA and SCL is
enabled or bypassed. If this bit is set to 0, the filtering is enabled; if it set to 1, the filtering is bypassed.
See the Sample Delay and Bit Trial Delay section.
See the Sample Delay and Bit Trial Delay section.
D4
CH0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D4
D3
REF_SEL
0
Analog Input Channel
No channel selected
Convert on V
Convert on V
Sequence between V
Convert on V
Sequence between V
Sequence between V
Sequence among V
Convert on V
Sequence between V
Sequence between V
Sequence among V
Sequence between V
Sequence among V
Sequence among V
Sequence among V
D2
FLTR
0
Rev. B | Page 20 of 28
IN0
IN1
IN2
IN3
IN0
IN0
IN0
IN1
IN0
IN0
IN0
IN1
IN0
IN1
IN2
, V
, V
, V
, V
, V
1
and V
and V
and V
IN1
and V
and V
IN1
and V
IN2
IN2
IN1
, and V
, and V
, and V
, and V
, V
D1
Bit trial delay
0
IN2
IN1
IN2
IN2
IN3
IN3
IN3
, and V
IN2
IN3
IN3
IN3
IN3
IN3
/V
REF
pin, and the device acts as a 3-channel
D0
Sample delay
0