AD6655 Analog Devices, AD6655 Datasheet - Page 52

• Manufacturer Part Number: AD6655
• Description: IF Diversity Receiver
• Manufacturer: Analog Devices

AD6655
Addr.
(Hex)
0x0D
0x10
0x14
0x16
0x17
0x18
Digital Feature Control Registers
0x100
0x101
0x102
0x103
Register
Name
Test Mode
(Local)
Offset Adjust
(Local)
Output Mode
Clock Phase
Control
(Global)
DCO Output
Delay
(Global)
VREF Select
(Global)
Sync Control
(Global)
f
Mix Control
(Global)
FIR Filter and
Output Mode
Control
(Global)
Digital Filter
Control
(Global)
S
/8 Output
Bit 7
(MSB)
Open
Open
Drive
strength
0 V to 3.3
V CMOS or
ANSI
LVDS;
1 V to 1.8
V CMOS or
reduced
LVDS
(global)
Invert
DCO clock
Open
Reference voltage
selection
Signal
monitor
sync
enable
Open
Open
Open
00 = 1.25 V p-p
01 = 1.5 V p-p
10 = 1.75 V p-p
11 = 2.0 V p-p
(default)
Bit 6
Open
Open
Output
type
0 = CMOS
1 = LVDS
(global)
Open
Open
Half-band
next sync
only
Open
Open
Open
Bit 5
Reset
PN long
sequence
Interleaved
CMOS
(global)
Open
Open
Open
Half-band
sync
enable
f
Open
Open
S
/8 start state
Offset adjust in LSBs from +31 to -32 (twos complement format)
Bit 4
Reset
PN short
sequence
Output
enable
bar (local)
Open
Open
NCO32
next sync
only
Open
Open
Rev. A | Page 52 of 88
Bit 3
Open
Open
Open
Open
NCO32
sync
enable
Open
FIR gain
0 = gain of
2
1 = gain of
1
Half-band
decimation
phase
(delay = 2500 ps × register value/31)
DCO clock delay
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
00000 = 0 ps
Bit 2
Output
invert
(local)
Open
Clock
divider
next
sync
only
Open
f
output
mix
disable
Spectral
reversal
S
/8
Input clock divider phase adjust
000 = no delay
010 = 2 input clock cycles
011 = 3 input clock cycles
100 = 4 input clock cycles
101 = 5 input clock cycles
110 = 6 input clock cycles
111 = 7 input clock cycles
001 = 1 input clock cycle
Output test mode
000 = off (default)
001 = midscale short
010 = positive FS
011 = negative FS
100 = alternating
101 = PN long sequence
110 = PN short sequence
111 = one/zero word
Bit 1
00 = offset binary
01 = twos complement
01 = gray code
11 = offset binary
(local)
Open
Clock
divider
sync
enable
f
sync only
Complex
output
enable
High-pass/
low-pass
select
S
/8 next
checkerboard
toggle
f
enable
Bit 0
(LSB)
Open
Master sync
enable
FIR filter
enable
Open
S
/8 sync
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x00
0xC0
0x00
0x00
0x00
0x01
Default
Notes/
Comments
When
enabled, the
test data is
placed on the
output pins
in place of
ADC output
data
Configures
the outputs
and the
format of
the data
Allows
selection of
clock delays
into the input
divider