AD7984 Analog Devices, AD7984 Datasheet - Page 19

• Manufacturer Part Number: AD7984
• Description: 18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN
• Manufacturer: Analog Devices

Specifications of AD7984

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1.33MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: CSP,SOP

CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when multiple AD7984s are connected
to an SPI-compatible digital host.
A connection diagram example using two AD7984s is shown in
Figure 32, and the corresponding timing is given in Figure 33.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
SDI(CS1)
SDI(CS2)
ACQUISITION
SDO
CNV
SCK
t
SSDICNV
t
HSDICNV
CONVERSION
t
CONV
t
EN
SDI
Figure 33. CS Mode, 4-Wire Without Busy Indicator Serial Interface Timing
Figure 32. CS Mode, 4-Wire Without Busy Indicator Connection Diagram
AD7984
D17
1
t
CNV
SCK
HSDO
D16
2
SDO
D15
3
t
DSDO
t
SCKL
t
Rev. A | Page 19 of 24
SCKH
16
SDI
t
SCK
AD7984
17
D1
CNV
SCK
t
CYC
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum possible
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7984
enters the acquisition phase and goes into standby mode. Each
ADC result can be read by bringing its SDI input low, which
consequently outputs the MSB onto SDO. The remaining data
bits are then clocked by subsequent SCK falling edges. The data
is valid on both SCK edges. Although the rising edge can be
used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided it has an acceptable
hold time. After the 18
high (whichever occurs first), SDO returns to high impedance
and another AD7984 can be read.
18
D0
ACQUISITION
t
SDO
ACQ
D17
19
CS2
CS1
CONVERT
DATA IN
CLK
DIGITAL HOST
D16
20
th
SCK falling edge or when SDI goes
34
35
D1
36
D0
t
DIS
AD7984