AD9626 Analog Devices, AD9626 Datasheet - Page 20

• Manufacturer Part Number: AD9626
• Description: 12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9626

• Resolution (bits): 12bit
• # Chan: 1
• Sample Rate: 250MSPS
• Interface: Par
• Analog Input Type: Diff-Uni
• Ain Range: 1 V p-p,1.25 V p-p,1.5 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9626
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR for a full-scale input signal
at a given input frequency (f
be calculated by
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 50).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9626.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 37, the power dissipated by the AD9626 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
By asserting PDWN (Pin 29) high, the AD9626 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9626 into its normal operational mode.
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 50 MHz, the
AD9626 assumes a standby state. In this case, the biasing network
Figure 50. Ideal SNR vs. Input Frequency and Jitter for 0 dBFS input Signal
SNR Degradation = 20 × log
130
120
110
100
90
80
70
60
50
40
30
1
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
ANALOG INPUT FREQUENCY (MHz)
10
A
) due only to aperture jitter (t
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
10
[1/2 × π × f
100
A
× t
J
]
16 BITS
14 BITS
12 BITS
1000
J
) can
Rev. 0 | Page 20 of 36
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9626 resumes normal
operation after allowing for the pipeline latency.
DIGITAL OUTPUTS
Digital Outputs and Timing
The off-chip drivers on the AD9626 are CMOS-compatible
output levels. The outputs are biased from a separate supply
(DRVDD), allowing isolation from the analog supply and easy
interface to external logic. The outputs are CMOS devices that
swing from ground to DRVDD (with no dc load). It is recom-
mended to minimize the capacitive load the ADC drives by
keeping the output traces short (<1 inch, for a total C
When operating in CMOS mode, it is also recommended to
place low value (20 Ω) series damping resistors on the data lines
to reduce switching transient effects on performance.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
If it is desired to change the output data format to twos comple-
ment, see the AD9626 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9626. The DCO+/DCO− signal is used to clock the
output data and is equal to the sampling clock (CLK) rate in
single port mode, and one-half the clock rate in interleaved
output mode. See the timing diagrams shown in Figure 2 and
Figure 3 for more information.
Out-of-Range
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OVRA/OVRB is a digital
output that is updated along with the data output corresponding
to the particular sampled input voltage. Thus, OVRA/OVRB
has the same pipeline latency as the digital data. OVRA/OVRB
is low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 51. OVRA/OVRB remains high until
the analog input returns to within the input range and another
conversion is completed. By logically AND-ing OVRA/OVRB
with the MSB and its complement, overrange high or under-
range low conditions can be detected.
Figure 51. OVRA/OVRB Relation to Input Voltage and Output Data
OVRA/OVRB
DATA OUTPUTS
1
0
0
0
0
1
1111
1111
1111
0000
0000
0000
1111
1111
1111
0000
0000
0000
1111
1111
1110
0001
0000
0000
OVRA/
OVRB
–FS – 1/2 LSB
–FS
–FS + 1/2 LSB
+FS – 1/2 LSB
+FS – 1 LSB
+FS
LOAD
< 5 pF).