AD7765 Analog Devices, AD7765 Datasheet
![no-image](/images/manufacturer_photos/0/0/56/analog_devices_sml.jpg)
AD7765
Specifications of AD7765
Available stocks
Related parts for AD7765
AD7765 Summary of contents
Page 1
... The external clock frequency applied to the AD7765 determines the sample rate, filter corner frequencies, and output word rate. The AD7765 device boasts a full band on-board FIR filter. The full stop-band attenuation of the filter is achieved at the Nyquist frequency. This feature offers increased protection from signals that lie above the Nyquist frequency being aliased back into the input signal bandwidth ...
Page 2
... Added Driving the Modulator Inputs Directly Section ............ 19 Changes to Synchronization Section, Added Figure 35 ............ 21 Changes to Power Modes Section, Added RESET / Mode Section, Added Figure 38 ................................................... 22 Changes to Daisy Chaining Section ............................................. 23 Changes to Using the AD7765 Section ........................................ 27 6/07—Revision 0: Initial Version AD7765 Functionality ................................................................... 21 Synchronization .......................................................................... 21 Overrange Alerts ........................................................................ 21 Power Modes ...
Page 3
... Differential amplifier inputs shorted Input amplitude = −0.5 dB Input amplitude = −0.5 dB Input amplitude = −6 dB Input amplitude = −6 dB Input amplitude = −6 dB 50.3 kHz Second-order terms Third-order terms Rev Page AD7765 = +25°C, normal power mode, using A 1 Specification Unit 115 dB typ 110 dB min 113.4 ...
Page 4
... AD7765 Parameter DC ACCURACY Resolution Integral Nonlinearity Zero Error Gain Error Zero Error Drift Gain Error Drift DIGITAL FILTER CHARACTERISTICS Pass-Band Ripple Pass Band 3 −3 dB Bandwidth 3 Stop Band 3 Stop-Band Attenuation Group Delay Decimate 128× Decimate 256× ANALOG INPUT Differential Input Voltage ...
Page 5
... See Terminology section. 2 SNR specifications in decibels are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified. Output data rate (ODR) = [(MCLK/2)]/decimation rate. That is, the maximum ODR for AD7765 = [(40 MHz/2)/128] = 156.25 kHz Tested with a 400 µA load current. ...
Page 6
... AD7765 TIMING SPECIFICATIONS 2 Table 3. Parameter Limit MIN MAX f 500 MCLK 40 f 250 ICLK × ICLK t 1 × ICLK 9 × SCO t 12 ...
Page 7
... RA12 RA11 RA10 RA9 RA8 Figure 3. AD7765 Register Write ≥8 × t SCO NEXT DATA READ FOLLOWING THE WRITE TO CONTROL REGISTER INSTRUCTION Figure 4. AD7765 Status Register Read Cycle Rev Page ST3 ST2 ST1 ST0 0 0 RA1 RA0 D15 D14 D1 STATUS REGISTER DON’ ...
Page 8
... AD7765 ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. A Table 4. Parameters GND GND GND DD V A+, V A− to GND − to GND Digital Input Voltage to GND GND 3 REF Input Current to Any Pin Except Supplies ...
Page 9
... SDO Serial Data Out. Data and status are output on this pin during each serial transfer. Each bit is clocked out on an SCO rising edge and is valid on the falling edge. See the AD7765 Interface section for further details. 13 SDI Serial Data In. The first data bit (MSB) must be valid on the next SCO falling edge after the FSI event is latched. ...
Page 10
... FSI Frame Sync Input. The status of this pin is checked on the falling edge of SCO. If this pin is low, then the first data bit is latched in on the next SCO falling edge. See the AD7765 Interface section for further details. 15 SYNC Synchronization Input. A falling edge on this pin resets the internal filter. This can be used to synchronize multiple devices in a system ...
Page 11
... Figure 10. Low Power Mode; FFT, 1 kHz, −0.5 dB Input Tone, 0 –25 –50 –75 –100 –125 –150 –175 75k 0 Figure 11. Low Power Mode; FFT, 1 kHz, −6 dB Input Tone, Rev Page AD7765 = 25°C. Linearity plots measured A 10k 20k 30k 40k 50k 60k 70k FREQUENCY (Hz) 128× Decimation Rate 5k ...
Page 12
... AD7765 0 –25 –50 –75 –100 –125 –150 –175 0 10k 20k FREQUENCY (Hz) Figure 12. Normal Power Mode; FFT, 1 kHz, −6 dB Input Tone, 256× Decimation Rate MCLK FREQUENCY (MHz) Figure 13. Normal Power Mode; Current Consumption vs. MCLK Frequency, 128× ...
Page 13
... Rev Page +85°C +25°C –40° 10k 15k 20k 25k 30k 35k 40k 45k 50k 16-BIT CODE SCALING Figure 21. Low Power Mode INL LOW SNR NORMAL SNR 0 64 128 192 DECIMATION RATE 1 kHz, −0.5 dB Input Tone AD7765 55k 59,535 256 ...
Page 14
... The AD7765 is tested using the CCIF standard, where two input frequencies near the top end of the input bandwidth are used. In this case, the second-order terms are usually distanced in frequency from the original sine waves and the third-order terms are usually at a frequency close to the input frequencies ...
Page 15
... ICLK decimation rate used. The AD7765 employs three FIR filters in series. By using different combinations of decimation ratios, data can be obtained from the AD7765 at three data rates. The first filter receives data from the modulator at ICLK where it is decimated 4× ...
Page 16
... DIGITAL FILTER RESPONSE NYQUIST = 78kHz Figure 27. Antialias Example Using the AD7765 in Normal Mode, Decimate 128× Using MCLK/2 = ICLK = 20 MHz Figure 26 shows the frequency response of the decimation filter when the AD7765 is operated with a 40 MHz MCLK in decimate 128× mode. Note that the first stop-band frequency occurs at Nyquist ...
Page 17
... 096 . 8 192 V REF + Diff ( ) As is inherent in Σ-Δ modulators, only a certain portion of this full reference may be used. In the case of the AD7765, 80% of the full differential reference can be applied to the modulator’s differential inputs. = Modulator _ Input . 8 192 FULLSCALE INPUT VOLTAGE ( 3.6855V ...
Page 18
... drive the ADC with differential signals. Figure 31 shows how a (pF) (pF) (pF) bipolar, single-ended signal biased around ground can drive the 8 AD7765 with the use of an external op amp, such as the AD8021 100 Rev Page and Pin V A− ...
Page 19
... MODULATOR SCO (O) FSI (I) SDI (I) Figure 33. Writing to the AD7765 Control Register Turning Off the On-Board The AD7765 modulator inputs must have a common-mode voltage of 2.048 V and adhere to the amplitudes as described in the AD7765 Input Structure section. An example of a typical circuit to drive the AD7765 for applications requiring excellent ac and dc performance is shown in Figure 34 ...
Page 20
... The OVR (overrange) bit is described in the Alerts section. • The LPWR bit is set to logic high when the AD7765 is operating in low power mode. See the Power Modes section for further details. • The DEC_RATE 1 and DEC_RATE 0 bits indicate the decimation ratio used ...
Page 21
... Timing Relative to MCLK SYNC , the digital filter needs time to settle before Following a valid data can be read from the AD7765. The user knows there is valid data on the SDO line by checking the FILTER-SETTLE status bit (see D7 in Table 9) that is output with each conversion result ...
Page 22
... All internal circuitry is reset. Apply a RESET pulse to the AD7765 after initial power-up of the device. The AD7765 RESET pin is polled by the rising edge of MCLK. The AD7765 device goes into reset when an MCLK rising senses the RESET input signal to be logic low. AD7765 comes out of RESET on the first MCLK rising edge that senses RESET to be logic high ...
Page 23
... Referring to Figure 39, note that the SDO line of AD7765 (A) provides the output data from the chain of AD7765 converters. Also, note that for the last device in the chain, AD7765 (D), the SDI pin is connected to ground. All of the devices in the chain must use common MCLK and SYNC signals ...
Page 24
... SCO periods indicates to the AD7765 device that there are more devices further on in the chain. This means that the AD7765 directs data that is input on the SDI pin to its SDO pin. This ensures that data is passed to the next device in the chain ...
Page 25
... CLOCKING THE AD7765 The AD7765 requires an external low jitter clock source. This signal is applied to the MCLK pin. An internal clock signal (ICLK) is derived from the MCLK input signal. The ICLK controls the internal operation of the AD7765. The maximum 20 MHz. ICLK frequency is To generate the ICLK, ...
Page 26
... AV 4 (Pin 25) DD • (Pin 24) DD • (Pin 21 layout decoupling scheme for these supplies, which connect to the right side of the AD7765, is shown in Figure 45. Note the star-point ground created at Pin 23 (PIN 25) GND AV DD PIN 23 V REF STAR-POINT ...
Page 27
... Values for gain and overrange thresholds can be written to or read from the respective registers at this stage. BIAS RESISTOR SELECTION The AD7765 requires a resistor to be connected between the RESET has R and AGNDx pins. The resistor value should be selected to BIAS give a current of 25 µ ...
Page 28
... AD7765 AD7765 REGISTERS The AD7765 has a number of user-programmable registers. The control register is used to set the functionality of the on-chip buffer and differential amplifier and provides an option to power down the AD7765. There are also digital gain and overrange threshold registers. Writing to these registers involves writing the register address followed by a 16-bit data word. The register addresses, details of individual bits, and default values are provided in this section ...
Page 29
... Assuming 4.096 V, the bit is then set when the REF input voltage exceeds approximately 6.55 V p-p differential. The overrange bit is set immediately if the analog input voltage exceeds 100 for more than four consecutive samples REF at the modulator rate. Rev Page AD7765 ...
Page 30
... AD7765 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY ORDERING GUIDE Model Temperature Range AD7765BRUZ 1 −40°C to +85°C AD7765BRUZ-REEL7 1 −40°C to +85°C EVAL-AD7765EDZ RoHS Compliant Part. 1 9.80 9.70 9. 4.50 4.40 4.30 6.40 BSC 0.65 BSC 1.20 MAX 0.30 0.20 0.19 SEATING 0.09 PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-153-AE Figure 48. 28-Lead Thin Shrink Small Outline Package [TSSOP] ...
Page 31
... NOTES Rev Page AD7765 ...
Page 32
... AD7765 NOTES ©2007–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06519-0-8/09(A) Rev Page ...