AD7982 Analog Devices, AD7982 Datasheet - Page 17

• Manufacturer Part Number: AD7982
• Manufacturer: Analog Devices

Specifications of AD7982

• Resolution (bits): 18bit
• # Chan: 1
• Sample Rate: 1MSPS
• Interface: Ser,SPI
• Analog Input Type: Diff-Uni
• Ain Range: (2Vref) p-p
• Adc Architecture: SAR
• Pkg Type: SOP

CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
This mode is usually used when a single AD7982 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 29, and the corresponding timing is given in
Figure 30.
With SDI tied to VIO, a rising edge on CNV initiates a
conversion, selects the CS mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
before the minimum conversion time elapses and then held
ACQUISITION
SDI = 1
SDO
CNV
SCK
t
CNVH
Figure 30. CS Mode, 3-Wire Without Busy Indicator Serial Interface Timing (SDI High)
Figure 29. CS Mode, 3-Wire Without Busy Indicator Connection Diagram (SDI High)
CONVERSION
t
CONV
VIO
SDI
t
EN
AD7982
CNV
SCK
D17
1
Rev. A | Page 17 of 24
t
HSDO
SDO
D16
2
t
CYC
ACQUISITION
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7982 enters the acquisition phase and powers
down. When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 18
CNV goes high (whichever occurs first), SDO returns to high
impedance.
D15
t
3
ACQ
t
DSDO
CONVERT
DATA IN
CLK
DIGITAL HOST
t
SCKL
t
SCKH
16
t
SCK
17
D1
18
D0
th
SCK falling edge or when
t
DIS
AD7982